Low Power Networks-on-Chip (eBook)

Cristina Silvano, Marcello Lajolo, Gianluca Palermo (Herausgeber)

eBook Download: PDF

2010 | 2011
XIX, 287 Seiten
Springer US (Verlag)
978-1-4419-6911-8 (ISBN)

Infos

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Inhalt

Preface 8
About the Editors 14
Contents 16
Contributors 18
Part I Low-Level Design Techniques 22
Chapter 1 Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections 23
1.1 Network on-Chip: Past, Present, and the Future 23
1.1.1 State of the Art in NoCs 24
1.1.1.1 Buses 24
1.1.1.2 Rings 24
1.1.1.3 Meshes 25
1.1.2 Issues and Challenges for the Future 25
1.1.2.1 Power and Energy 25
1.1.2.2 Heterogeneity 26
1.2 Proposed Hybrid Packet/Circuit Switched NoC 27
1.2.1 Circuit-Switched Data with Packet-Switched Arbitration NoC 27
1.2.2 Circuit Innovations for Circuit/Packet Switched Network Arbitration 30
1.2.3 Data Transmission Circuit Innovations 33
1.3 NoC Measurements and Tradeoffs in 45nm CMOS 35
1.4 Conclusion 39
References 39
Chapter 2 Run-Time Power-Gating Techniques for Low-Power On-Chip Networks 41
2.1 Introduction 41
2.2 On-Chip Virtual-Channel Router 42
2.2.1 Target Router Architecture 42
2.2.2 Power Analysis of the Target Router Architecture 44
2.3 Previous Work on Low-Power Techniques 45
2.3.1 Voltage and Frequency Scaling Techniques 45
2.3.2 Power Gating Techniques 46
2.3.2.1 Coarse-Grained Power-Gating Techniques 46
2.3.2.2 Fine-Grained Power Gating Techniques 46
2.3.2.3 Power Gating for Interconnection Networks 47
2.4 Fine-Grained Power Gating Router 48
2.4.1 Power Domain Partitioning 48
2.4.2 Power Domain Implementation 49
2.4.3 Wakeup Latency Estimation 50
2.5 Wakeup Control Methods 51
2.5.1 Wakeup Latency Impact 51
2.5.2 Look-Ahead Method 52
2.5.3 Look-Ahead with Ever-On Method 54
2.5.4 Look-Ahead with Active Buffer Window Method 54
2.6 Experimental Evaluations 55
2.6.1 Simulation Environment 55
2.6.2 Performance Impact 57
2.6.3 Leakage Power Reduction 59
2.7 Summary 60
References 62
Chapter 3 Adaptive Voltage Control for Energy-Efficient NoC Links 64
3.1 Introduction 64
3.2 Methods for Energy-Efficient On-Chip Links 65
3.2.1 Metrics for Energy Efficiency 65
3.2.2 Datalink Layer Techniques 66
3.2.2.1 Bus Invert and Extended Bus Invert Coding 66
3.2.2.2 Frequent Value Coding 66
3.2.2.3 Crosstalk Avoidance Coding 67
3.2.2.4 Asymptotic Zero-Transition Coding 67
3.2.3 Physical Layer Techniques 68
3.2.3.1 Low-Swing Signaling 68
3.2.3.2 Differential Signaling 69
3.2.3.3 Repeater Insertion 69
3.2.3.4 Dual-Voltage Buffers 70
3.2.3.5 Pulsed Transmission 70
3.2.3.6 Current Mode Signaling 71
3.2.3.7 Globally Asynchronous Locally Synchronous (GALS) Signaling 71
3.2.3.8 Quasi-Resonant Interconnect 71
3.2.3.9 Adaptive Link Voltage Scaling 72
3.2.4 Other Methods 72
3.2.4.1 Integrating Double Sampling with Adaptive Voltage Scaling 72
3.2.4.2 Combining Error Control Coding with Adaptive Voltage Scaling 72
3.3 Lookahead-Based Transition-Aware Link Voltage Control 73
3.3.1 Lookahead Transmitter Design 74
3.3.2 HI/LO Voltage Selection 77
3.3.3 Performance Evaluation 78
3.3.3.1 Comparison with Traditional Two-Inverter Driver 79
3.3.3.2 Comparison with Adaptive Voltage Driver 81
3.3.3.3 Comparison with Prior Dual-Voltage Switching Method 83
3.3.4 Limitations 84
References 86
Chapter 4 Asynchronous Communications for NoCs 89
4.1 Introduction 90
4.1.1 Variability 91
4.1.2 Power Consumption 92
4.1.3 Chapter Structure 93
4.2 History of Asynchronous Communications Before the NoC Era 94
4.3 Token-Based View of Communication 95
4.4 Basics of Asynchronous Signalling 97
4.4.1 Signalling Techniques 97
4.4.2 Handshake Protocols 98
4.4.3 Channel Types 99
4.5 Delay-Insensitive Data Communication 100
4.5.1 Dual-rail 100
4.5.2 1-of-N and M-of-N 101
4.5.3 Single Transition Codes 104
4.6 Delay-Sensitive Communication 105
4.6.1 Bundled-Data Encoding 105
4.6.2 Single-Track Signalling 106
4.6.3 Pulse-Based Signalling 106
4.7 SEU Resilient Codes 107
4.7.1 Phase Encoding 107
4.7.2 Data-Reference Codes 108
4.7.3 Summary on Codes 109
4.8 Pipelining 110
4.8.1 Paired Handshake 111
4.8.2 Serial vs. Parallel Links 112
4.9 Networks-on-Chip 113
4.10 Synchronizers 115
4.10.1 Design of a Simple Synchronizer 116
4.11 Routers 118
4.11.1 Arbiters 119
4.12 CAD Issues 120
4.12.1 Logic Synthesis 120
4.12.2 Syntax-Driven Design 121
4.12.3 Example of Synthesis Using Petrify 121
4.13 Conclusions 124
References 124
Part II System-Level Design Techniques 128
Chapter 5 Application-Specific Routing Algorithms for Low Power Network on Chip Design 129
5.1 Introduction 129
5.2 Background on Routing Algorithms and Power Dissipation 131
5.2.1 Classification of Routing Algorithms 131
5.2.2 Wormhole Switching and Deadlock 132
5.2.3 Basic Components of a Routing Algorithm 133
5.2.3.1 Routing Function 133
5.2.3.2 Selection Function 134
5.2.4 Routing Logic and Hardware Implications 135
5.2.5 Region Concept in NoC 136
5.2.6 Network Energy and Routing Algorithms 137
5.2.7 Common Performance Metrics 138
5.3 Terminology and Definitions 138
5.3.1 Basic Definitions 138
5.3.2 Channel Dependency Graph and Deadlock Freedom 139
5.3.3 Application-Specific Channel Dependency Graph 140
5.3.4 Routing Adaptivity 141
5.4 APSRA Design Methodology 141
5.4.1 APSRA by Example 141
5.4.2 Main Algorithm 144
5.4.3 Cutting Edge with Minimum Loss of Adaptivity 144
5.4.4 Routing Tables 147
5.4.4.1 Routing Table Compression 147
5.5 Performance Evaluation of APSRA 149
5.5.1 Traffic Scenarios 149
5.5.2 Adaptivity Analysis 151
5.5.3 Simulation Based Evaluation 152
5.5.3.1 Homogeneous 2D Mesh NoC 153
5.5.3.2 NonHomogeneous 2D Mesh NoC with Regions 155
5.6 Cost, Power Dissipation and Energy Consumption Analysis 159
5.6.1 Generic Router Architecture 159
5.6.2 Area and Power Dissipation 160
5.6.3 Energy Consumption 162
5.7 Conclusions 163
References 164
Chapter 6 Adaptive Data Compression for Low-Power On-Chip Networks 167
6.1 Introduction 167
6.2 Related Work 169
6.3 Data Compression In On-Chip Networks 170
6.3.1 On-Chip Network Architecture 170
6.3.2 Compression Support 172
6.3.3 Table Organization 174
6.4 Optimizing Compression 174
6.4.1 Shared Table Structure 174
6.4.2 Shared Table Consistency Management 176
6.4.3 Increasing Compression Effectiveness 176
6.5 Methodology 178
6.6 Experimental Results 179
6.6.1 Compressibility and Value Pattern 180
6.6.2 Effect on Power Consumption 182
6.6.3 Effect on Packet Latency 184
6.6.4 Compression Table Area Analysis 186
6.6.5 Comparison with Wide/Long-Channel Networks 187
6.7 Conclusion 188
References 189
Chapter 7 Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study 191
7.1 Introduction 191
7.2 Related Work 193
7.3 The Target Application 194
7.4 NoC Design and Optimization 197
7.4.1 Cost-Optimized Mapping 198
7.4.2 Setting Link Capacities 200
7.5 Experimental Results 203
7.5.1 Target Router Architecture 204
7.5.2 Synthesis Results 206
7.6 Summary and Conclusions 209
References 210
Part III Future and Emerging Technologies 212
Chapter 8 Design and Analysis of NoCs for Low-Power 2D and 3D SoCs 213
8.1 Introduction 213
8.2 Architecture with Voltage Island Support 216
8.2.1 2D SoC Architecture 216
8.3 3D SoC Architecture 218
8.4 Design Approach 218
8.4.1 Synthesis Problem Formulation 219
8.5 Synthesis Algorithm for 2D ICs with VI Shutdown 220
8.6 Extension for 3D ICs 224
8.7 Experimental Results 225
8.7.1 Design of 2D ICs 225
8.7.2 Baseline Comparison of 2D and 3D ICs 230
8.7.3 Comparison for Different Number of Voltage and Frequency Islands 230
8.7.4 Analysis of Results 233
8.8 Conclusions 234
References 234
Chapter 9 CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study 237
9.1 Introduction 238
9.2 CMOS Nanophotonic Technologies 240
9.2.1 Overview 241
9.2.2 Sources 242
9.2.3 Waveguides, Splitters, Couplers and Connectors 243
9.2.4 Detectors 244
9.2.5 Technology for Intra- and Inter-Chip Communication 244
9.3 Nanophotonic Network Principles 245
9.3.1 Electrical Interconnects 246
9.3.2 Optical Interconnect 247
9.3.3 Photonic Network Fundamentals 249
9.3.4 Optical Arbitration 250
9.3.5 Optical Barriers 252
9.4 Corona: A Nanophotonic Case Study 253
9.4.1 Corona Architecture 254
9.4.2 Experimental Setup 261
9.4.3 Performance Evaluation 263
9.5 Summary 265
References 266
Chapter 10 RF-Interconnect for Future Network-On-Chip 269
10.1 Introduction 269
10.2 Interconnect Problem in Future Information Processor 270
10.3 How Can RF Help? 272
10.4 Expected Performance of RF-I with Scaling 275
10.5 Implementation Examples 275
10.5.1 On-Chip Multi-Carrier Generation 275
10.5.2 On-Chip RF-Interconnect 277
10.5.3 3D IC RF-Interconnect 284
10.6 Impact of RF-I in Future SoC/NoC Architecture 286
10.7 Future RF-I Research Direction 287
References 293
Index 295

Produkt-Details

• Erscheint lt. Verlag: 24.9.2010
• Zusatzinfo: XIX, 287 p.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Nachrichtentechnik
• Schlagworte: Embedded Systems • High Speed Interconnect • Low Power Design • Network on Chip • On-chip Communication Architectures • System-on-Chip
• ISBN-10: 1-4419-6911-X / 144196911X
• ISBN-13: 978-1-4419-6911-8 / 9781441969118