Low Power Networks-on-Chip
Seiten
2014
Springer-Verlag New York Inc.
978-1-4899-9437-0 (ISBN)
Springer-Verlag New York Inc.
978-1-4899-9437-0 (ISBN)
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.
Erscheint lt. Verlag | 20.11.2014 |
---|---|
Zusatzinfo | XIX, 287 p. |
Verlagsort | New York |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
Technik ► Elektrotechnik / Energietechnik | |
ISBN-10 | 1-4899-9437-8 / 1489994378 |
ISBN-13 | 978-1-4899-9437-0 / 9781489994370 |
Zustand | Neuware |
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