Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications (eBook)

Madhav Datta, Takayuki Ohba, Tetsuya Osaka, Yosi Shacham-Diamand (Herausgeber)

eBook Download: PDF

2009 | 2009
XX, 552 Seiten
Springer New York (Verlag)
978-0-387-95868-2 (ISBN)

Infos

In Advanced ULSI interconnects - fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous 'Moore's law' which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g. , speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.

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In Advanced ULSI interconnects - fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous "e;Moore's law"e; which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g. , speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.

Inhalt

Preface 6
Acknowledgments 10
Contents 11
Contributors 15
Part I Introduction 19
1 Challenges in ULSI Interconnects Introduction to the Book 20
1.1 Material Issues in Cu Interconnects 22
1.2 Interconnect Performance Issues 23
1.3 Interconnect Process Issues 25
References 28
Part II Technology Background 29
2 MOS Device and Interconnects Scaling Physics 30
2.1 Device Fundamentals 30
2.1.1 The MOSFET Transistor 30
2.1.1.1 Basic Device Physics 30
2.1.1.2 Technology 32
2.1.2 Current Regimes 32
2.1.3 Mobility and Carrier Velocity 35
2.2 Digital Signal Propagation 36
2.2.1 Gate Delay 36
2.2.2 Gate Delay Versus Interconnect Delay 37
2.2.3 Trends in CMOS Miniaturization 38
2.2.3.1 Moore's Law 38
2.2.3.2 Roadmaps 40
2.2.3.3 Scaling Theory 42
2.2.3.4 Scaling and Power Dissipation 44
2.3 New Device Structures and Materials 47
2.3.1 Strained-Silicon MOSFETs 47
2.3.2 Silicon-On-Insulator (SOI) 49
2.3.3 Strained Silicon and SOI 49
2.3.4 Germanium and III--V Channel Devices 50
2.3.5 Novel MOSFET Devices 51
References 53
3 Interconnects in ULSI Systems: Cu Interconnects Electrical Performance 54
3.1 Introduction 54
3.2 On-Chip Interconnect Requirements 54
3.3 Interconnect Metrics 58
3.4 Circuit Models of Interconnect 60
3.4.1 Ideal Interconnect 60
3.4.2 Capacitive Interconnect 61
3.4.3 Resistive Interconnect 63
3.4.4 Inductive Interconnect 65
3.5 The Interconnect Scaling Problem 67
3.6 Design Approaches and Techniques for Addressing Interconnect Problems 70
3.6.1 Metallization Stack Design 71
3.6.2 Repeater Insertion and Other Circuit Techniques 71
3.6.3 Layout Optimization Techniques 72
3.6.4 Circuit Architecture 73
3.7 Power Supply Interconnect 73
3.8 Summary 74
References 75
4 Electrodeposition 78
4.1 Introduction 78
4.2 Key Considerations 79
4.3 Pulse Plating and Pulse Reverse Plating 81
4.4 Electrodeposition of Copper 82
4.4.1 Electrodeposition Process for Copper Interconnects 83
4.5 Concluding Remarks 84
References 84
5 Electrophoretic Deposition 87
5.1 Electrophoresis and Electrophoretic Deposition 87
5.1.1 Process Limitations 87
5.1.2 Theoretical Basis 88
5.2 Potential Applications 88
5.2.1 Conducting Lines 89
5.2.2 Embedded Passive Components 89
5.2.3 Solid Electrolyte Capacitors 91
References 92
6 Wafer-Level 3D Integration for ULSI Interconnects 93
6.1 Introduction 93
6.2 Types of 3D Integration 94
6.3 BEOL-Based Wafer-Level 3D Processing Considerations 98
6.4 Wafer-Level 3D Design Opportunities 100
6.5 Future Projections 102
References 102
Part III Interconnect Materials 105
7 Diffusion Barriers for Ultra-Large-Scale Integrated Copper Metallization 107
7.1 The Motivation for the Introduction of Copper Metallization 107
7.2 Difficulties of Implementing Cu Metallization 108
7.2.1 Copper Diffusion Through and Degradation of the Dielectric 109
7.2.2 Copper Adhesion to the Dielectric 110
7.2.3 Copper Passivation 110
7.2.4 Copper Diffusion in and Reaction with Si 110
7.2.4.1 Diffusion 110
7.2.4.2 Precipitation 111
7.2.4.3 Silicides 111
7.2.5 Processing 112
7.3 Diffusion Barriers 112
7.3.1 Approaches and Examples 113
7.3.1.1 Passive Metallic Thin Films 113
7.3.1.2 Thermodynamically Stable Barriers 115
7.3.1.3 ''Stuffed'' Barriers 116
7.3.1.4 Sacrificial Barriers 117
7.3.1.5 Self-forming Barriers 118
7.3.1.6 Single Crystalline Barriers 118
7.3.1.7 Amorphous Barriers 119
7.3.1.8 Self-assembled Molecular Layers 119
7.3.2 Deposition Methods 120
7.4 Evaluation of Diffusion Barriers for Cu Metallization 121
7.5 Summary and Future Trends 128
References 130
8 Silicides 135
8.1 Introduction 135
8.2 TiSi 2 138
8.3 CoSi 2 139
8.4 NiSi 139
8.5 SiGe Incorporation into Silicide/Si Contacts 141
References 142
9 Materials for ULSI metallization -- Overview of ElectricalProperties 145
9.1 Introduction 145
9.2 Large-Grained Cu Interconnects 147
9.2.1 Abnormal Grain Growth of Cu Thin Films 147
9.3 Grain Growth Mechanism of Cu Thin Films 149
9.3.1 Self-formation of Nano-scale Ti Diffusion Barrier Layers in Cu(Ti) Alloy Films 152
9.4 Summary 154
References 155
10 Low-k Materials and Development Trends 158
10.1 Introduction 158
10.2 Change of Insulator Between Wiring 158
10.3 Low-k Materials Trends and Their Condition for Practical Usage 159
10.4 Technical Issues of Porous Low-k Materials and Their Provisions 160
10.4.1 Mechanical Properties 161
10.4.2 Adsorption 161
10.4.3 Heat Conduction 161
10.4.4 Relationship with Other Materials 161
10.5 Ultimate Porous Low-k Material 162
References 164
11 Electrical and Mechanical Characteristics of Air-Bridge Cu Interconnects 165
11.1 Introduction 165
11.2 Methods of Simulation 166
11.2.1 Model Structure 166
11.2.2 Electrical Simulation 168
11.2.3 Stress Simulation 169
11.2.4 Calculation of Effective Elastic Modulus, B 172
11.3 Simulation Results and Discussion 172
11.3.1 Effective Dielectric Constant, keff 172
11.4 Volume-Averaged Stresses 173
11.4.1 Stresses in Single-Via Structure 174
11.4.2 Stresses in Multi-Level Structure 175
11.4.3 Effective Elastic Moduli, B 177
11.5 Conclusions 177
References 178
12 ALD Seed Layers for Plating and Electroless Plating 180
12.1 Introduction 180
12.2 Thermal and Plasma-Enhanced ALD 182
12.3 Palladium on Noble Metal 184
12.4 Palladium on Tetrasulfide Silane 184
12.5 Electroless Deposition of Cu on PA-ALD Pd 187
12.6 Conclusions 189
References 189
Part IV Deposition Processes for ULSI Interconnects 191
13 Electrochemical Processes for ULSI Interconnects 193
13.1 Introduction 193
13.2 Copper Plating Chemistry 196
13.2.1 Copper Electrodeposition for Trench Filling 196
13.2.1.1 Bath Composition for Void-Free Filling 196
13.2.1.2 Copper Deposition Mechanism and Kinetics 197
13.2.1.3 Chemistry of Copper Plating Bath 198
13.2.1.4 Reaction Mechanism: Effect of Additives 199
13.2.1.5 Mechanism of Void-Free Filling Effect of Additives 203
13.2.2 Copper Electroless Deposition for Trench Filling 204
13.2.2.1 Mechanism of Electroless Copper Deposition 205
13.2.2.2 Superfilling by Electroless Copper Deposition 206
13.3 Electrochemical Process for Seed Layer Formation 208
13.3.1 Electroless Deposition for Formation of Seed Layers 208
13.3.2 Seedless Copper Electrodeposition on Barrier Materials 209
13.3.3 Electroless Deposition for Barrier Layer Formation and Seedless Copper Filling 210
References 211
14 Atomic Layer Deposition (ALD) Processes for ULSIManufacturing 216
14.1 Introduction 216
14.2 Applications of Atomic Layer Deposition in ULSI Manufacturing 219
14.2.1 Front-End-of-Line (FEOL) Applications 220
14.2.2 Middle-of-Line (MOL) Applications 221
14.2.3 Back-End-of-Line (BEOL) Applications 223
14.3 Plasma-Assisted Atomic Layer Deposition (PAALD) 226
14.4 Challenges for Adapting Atomic Layer Deposition in ULSI Manufacturing 226
References 227
15 Electroless Deposition Approaching the Molecular Scale 230
15.1 Introduction 230
15.2 Fundamentals 232
15.2.1 Steering Macroscopic Electroless Deposition 233
15.2.2 What Makes Nanoscale Deposition Special? 234
15.3 Scaling Down Macroscopic Electroless Deposition 235
15.3.1 Sensitization, Pd and Pd/Sn Colloids 235
15.3.2 Confinement Plating 237
15.3.3 Biomolecules as Templates 238
15.3.4 Confinement Plating in Biomolecules 240
References 241
Part V Modeling 245
16 Modeling Superconformal Electrodeposition Using an Open Source PDE Solver 246
16.1 Introduction 246
16.2 Governing Equations 249
16.3 Level Set Equations 252
16.4 Numerical Discretization 253
16.5 FiPy Example 256
16.6 Summary 259
References 259
Part VI Electrochemical Process Integration 261
17 Introduction to Electrochemical Process Integration for Cu Interconnects 263
17.1 Introduction 263
References 266
18 Damascene Concept and Process Steps 268
18.1 Damascene Process 268
18.2 Low-k Integration Challenges 271
18.3 Damage-Free Process 274
18.4 Biography 276
References 277
19 Advanced BEOL Technology Overview 279
19.1 Introduction 279
19.2 Low-k Materials for Each Technology Node 281
19.3 Metallization Issues 282
19.4 BEOL Technology for 90nm Technology Node 283
19.4.1 Introduction 283
19.4.2 Interconnects Structure and Low-k Film Characteristics 284
19.4.3 Dual Damascene Process 285
19.5 BEOL Technology for 65nm/45nm Technology Node 288
19.5.1 Introduction/Integration Issues 288
19.5.2 Application of Advanced EB Curing Process 289
19.6 Summary and Future Trends 294
19.6.1 Summary 294
19.6.2 Robust Process Development 295
19.6.3 Patterned Low-k Films Characterization 297
19.7 Biography 298
References 299
20 Lithography for Cu Damascene Fabrication 303
20.1 Introduction 303
20.2 Lithography Process for Cu Damascene Interconnects 303
20.2.1 Process with Photoresist (PR) Mask 306
20.3 Processes with Hard Masks (HM) 309
20.4 Summary 312
References 313
21 Physical Vapor Deposition Barriers for Cu metallization - PVD Barriers 315
21.1 Necessity of Diffusion Barrier Layer 315
21.2 Metallurgy for Barrier Material Selection 316
21.3 Deposition Technique 320
21.4 Self-Forming Technique 321
21.4.1 Driving Force 321
21.4.2 Kinetics 324
References 324
22 Low-k Dielectrics 328
22.1 Introduction 328
22.2 Basic Properties of Low-k Films 330
22.2.1 Post-curing Techniques for Low-k Hardening 333
22.3 Innovations of Low-k Material and Process 335
22.4 Future Trends on CAP Dielectrics 340
22.5 Summary 340
22.6 Acknowledgments 341
References 342
23 CMP for Cu Processing 346
23.1 CMP Review 346
23.1.1 Chemical Mechanical Planarization 346
23.1.2 Application of CMP 346
23.2 CMP System 347
23.3 Cu-CMP 348
23.3.1 Application 348
23.3.2 Cu Polish Principle and Performances 351
23.3.3 Slurry Requirements 351
23.3.4 Monitors 352
23.3.5 Cleaning 353
23.4 General Principle of Cu-CMP 353
23.4.1 Several Planarization Technologies 354
23.4.2 CMP (Chemical Mechanical Polisher): Preston's Law 356
23.4.3 ECP (Electro Chemical Polishing): Faraday's Law 356
23.4.4 ECMP (Electrical Chemical Mechanical Polisher): Preston and Faraday's Laws 357
23.4.5 CE (Chemical Etching): Dissolution Law 358
23.5 General Principle of Planarization 358
References 359
24 Electrochemical View of Copper Chemical--MechanicalPolishing (CMP) 361
24.1 Introduction 361
24.2 Ammonium Hydroxide-Based CMP Slurry 363
24.3 Nitric Acid (HNO 3 )-Based CMP Slurry 366
24.4 Peroxide-Based CMP Slurries 369
24.5 Carbonate- and Sorbate-Based Solutions 374
References 378
25 Copper Post-CMP Cleaning 381
25.1 Introduction 381
25.2 Summary 387
References 387
Part VII Electrochemical Processes and Tools 389
26 Electrochemical Processing Tools for Advanced Copper Interconnects: An Introduction 390
26.1 Dual Damascene Process for Electroplated Copper Interconnects 390
26.2 Tooling Requirements 391
26.3 45 nm Node and Beyond: Novel Processes and Tools 392
26.3.1 Electropolishing for Planarization 393
26.3.2 Electroless Processes for Damascene Capping 394
26.4 Concluding Remarks 395
References 396
27 Electrochemical Deposition Processes and Tools 398
27.1 Introduction 398
27.2 Electrochemical Processing Equipment 398
27.2.1 Equipment Automation and Wafer Handling 398
27.2.2 Processing Chambers 400
27.2.3 Tool Configuration 401
27.3 Electrochemical Processes 401
27.3.1 Damascene Copper Electrodeposition 402
27.3.2 Through-Mask Electrodeposition 406
27.3.3 Electrografting 407
27.3.4 Electrophoretic Deposition 408
27.4 Summary 409
27.5 Biographical Sketches 409
References 409
28 Electroless Deposition Processes and Tools 413
28.1 Introduction 413
28.2 Electroless Copper Deposition 413
28.2.1 Copper Deposition Chemistry 414
28.2.2 Electroless Copper for Seeding Barriers 416
28.2.3 Surface Activation Using Palladium 416
28.2.4 Surface Activation Through Sensitization 417
28.2.5 Direct Surface Activation Using Copper 417
28.2.6 Electroless Copper for Gap Fill 418
28.2.7 Copper Deposition Process Summary 418
28.3 Electroless Nickel Deposition 419
28.3.1 Nickel Deposition Chemistry 420
28.3.2 Substrate Activation 421
28.3.3 Palladium Activation of Copper Substrate 421
28.3.4 Self-Activation of Copper Substrate 422
28.3.5 Activation of Aluminum Substrates 422
28.3.6 Nickel Deposition Process Summary 425
28.4 Electroless Gold Deposition 425
28.4.1 Cyanide-Based Gold Deposition 425
28.4.2 Immersion Deposition 426
28.4.3 Autocatalytic Deposition 426
28.4.4 Substrate (Nickel)-Catalyzed Deposition 428
28.4.5 Non-cyanide Gold Deposition 428
28.5 Electroless Deposition Equipment 429
28.6 Biographical Sketches 430
References 430
29 Tools for Monitoring and Control of Bath Components 434
29.1 Introduction 434
29.2 Chemical Constituent Analysis 435
29.2.1 Titration 435
29.2.2 X-ray Fluorescence 436
29.2.3 Electroanalytical Techniques 436
29.2.3.1 Cyclic Voltammetric Stripping 436
29.2.3.2 CPVS 437
29.2.3.3 PCGA 438
29.2.3.4 Chronoamperometry 438
29.2.4 Photometric Techniques 439
29.2.5 Probes and Electrodes 439
29.2.6 Liquid Chromatography 439
29.2.7 Mass Spectrometry 440
29.2.8 Analytical Techniques Summary 440
29.3 Constituent Replenishment 441
29.4 System Design 441
29.5 Biographical Sketches 442
References 443
30 Processes and Tools for Co Alloy Capping 444
30.1 Introduction 444
30.2 Co Alloy Capping Applications 444
30.3 Film Properties and Requirements 446
30.4 Process Sequence and Integration 448
30.5 Deposition Chemistry 449
30.6 Co Alloy Capping System 450
30.7 Conclusion 454
References 454
31 Advanced Planarization Techniques 457
31.1 Introduction 457
31.2 Electrochemical Polishing 458
31.2.1 Conventional Copper Electropolishing Processes 458
31.3 Novel Electropolishing Approaches 459
31.4 Electrochemical Mechanical Deposition 460
31.4.1 Planarization Mechanism of ECMD 461
31.5 ElectroChemical Mechanical Planarization (ECMP) 467
31.5.1 Planarization Mechanism of ECMP 467
References 470
Part VIII Metrology 474
32 Integrated Metrology (IM) History at a Glance 475
32.1 Introduction 475
32.2 Integrated Metrology (IM) Technology 477
32.3 IM CLC 481
32.4 CLC Results 484
32.5 Qualitative View for ITM Return on Investment 484
32.5.1 Capital Investment 486
32.5.2 Labor Reduction 486
32.5.3 Process 487
32.5.3.1 Rework 487
32.5.3.2 Reduction of Test Wafer Usage 487
32.5.3.3 Excursion Detection 487
32.5.3.4 Yield 487
32.6 Manufacturing 487
32.6.1 Cycle Time Reduction 487
32.6.2 Reduced Downtime After PM and Faster Tool Qualification 488
32.7 Shallow Trench Isolation (STI) 488
32.8 Pre-metal Dielectric (PMD) 488
32.9 Copper 489
32.10 Future Considerations 489
32.11 Summary 490
References 490
33 Thin Film Metrology X-ray Methods 492
33.1 X-Ray Fluorescence (XRF) 492
33.2 X-Ray Reflectometry (XRR) 493
33.3 Small-Angle X-Ray Scattering (SAXS) 495
Part IX Summary and Foresight 498
34 Emerging Nanoscale Interconnect Processing Technologies: Fundamental and Practice 499
34.1 Introduction 499
34.2 Nanoscale Copper Interconnect Architectures 500
34.2.1 Hyper-integration Interconnects 502
34.2.2 Die-to-Die Integration 503
34.2.3 Die-to-Wafer Integration 503
34.2.4 Wafer-to-Wafer Integration 504
34.3 Nanoscale Interconnects Technology: Moletronics 505
34.3.1 Carbon Nanotubes 506
34.3.2 Geometric and Electronic Structures of CNTs 508
34.3.3 Mechanical and Thermal Properties of CNTs 509
34.3.4 Interconnect Applications of CNTs 510
34.3.4.1 Tube-Tube Junctions 510
34.3.4.2 Tube--Metal Contacts 512
34.3.5 Alternatives Molecular Systems 513
34.3.5.1 Charge Transport Mechanisms 513
34.3.5.2 Self-assembly Techniques 514
34.3.6 Self-assembly Techniques 516
34.4 Nanoscale Interconnects Technology: Spintronics 516
34.5 Prolog: Electroplating as Enabling Technology 518
34.6 Conclusions 520
References 520
35 Self-Assembly of Short Aromatic Peptides: From Amyloid Fibril Formation to Nanotechnology 525
35.1 The Formation of Nanostructures by Short Aromatic Peptides 525
35.1.1 Bio-inspired Biological Nano-assemblies 525
35.1.2 The Role of Aromatic Residues in the Self-Assembly of Amyloid Nano-fibrils 525
35.1.3 The Identification of Aromatic Dipeptide Nanotubes (ADNT) 527
35.2 Technological Applications of the Peptide Tubes 528
35.3 The Formation of Nano-spheres by Related Aromatic Dipeptides 529
35.4 Other Modified Aromatic Homo-dipeptides 529
35.5 The Technological Advantages of Peptide Building Blocks 530
35.6 Summary 530
References 531
Index 532

Produkt-Details

• Erscheint lt. Verlag: 19.9.2009
• Zusatzinfo: XX, 552 p.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Naturwissenschaften ► Chemie ► Physikalische Chemie
• Themenwelt: Naturwissenschaften ► Chemie ► Technische Chemie
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Maschinenbau
• Schlagworte: Chemistry • CMOS • Development • Electrochemistry • Integrated circuit • Interconnect • Manufacturing • Modeling • nanotechnology • scaling • Vapor • Wafer
• ISBN-10: 0-387-95868-1 / 0387958681
• ISBN-13: 978-0-387-95868-2 / 9780387958682