Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Seiten
2011
Springer-Verlag New York Inc.
978-1-4614-0871-0 (ISBN)
Springer-Verlag New York Inc.
978-1-4614-0871-0 (ISBN)
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
| Zusatzinfo | XXII, 170 p. |
|---|---|
| Verlagsort | New York, NY |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 1-4614-0871-7 / 1461408717 |
| ISBN-13 | 978-1-4614-0871-0 / 9781461408710 |
| Zustand | Neuware |
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