Nanometer CMOS ICs
Springer-Verlag New York Inc.
978-1-4020-8332-7 (ISBN)
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Foreword. Preface. Overview of symbols. List of physical constants. 1 Basic Principles. 1.1 Introduction. 1.2 The field-effect principle. 1.3 The inversion-layer MOS transistor. 1.4 Derivation of simple MOS formulae. 1.5 The back-bias effect (back-gate effect, body effect) and the effect of forward-bias. 1.6 Factors which characterise the behaviour of the MOS transistor. 1.7 Different types of MOS transistors. 1.8 Parasitic MOS transistors. 1.9 MOS transistor symbols. 1.10 Capacitances in MOS structures. 1.11 Conclusions. 1.12 References. 1.13 Exercises. 2 Geometrical-, physical- and field-scaling impact on MOS transistor behaviour. 2.1 Introduction. 2.2 The zero field mobility. 2.3 Carrier mobility reduction. 2.4 Channel length modulation. 2.5 Short- and narrow-channel effects. 2.6 Temperature influence on carrier mobility and threshold voltage. 2.7 MOS transistor leakage mechanisms. 2.8 Conclusions. 2.9 References. 2.10 Exercises. 3 Manufacture of MOS devices. 3.1 Introduction. 3.2 Different substrates (wafers) as starting material. 3.3 Lithography in MOS processes. 3.4 Etching. 3.5 Oxidation. 3.6 Deposition. 3.7 Diffusion and ion implantation. 3.8 Planarisation. 3.9 Basic MOS technologies. 3.10 Conclusions. 3.11 References. 3.12 Exercises. 4 CMOS circuits. 4.1 Introduction. 4.2 The basic nMOS inverter. 4.3 Electrical design of CMOS circuits. 4.4 Digital CMOS circuits. 4.5 CMOS input and output (I/O) circuits. 4.6 The layout process. 4.7 Conclusions. 4.8 References. 4.9 Exercises. 5 Special circuits, devices and technologies. 5.1 Introduction. 5.2 CCD and CMOS image sensors. 5.3 Power MOSFET transistors. 5.4 BICMOS digital circuits. 5.5 Conclusions. 5.6 References. 5.7 Exercises. 6 Memories. 6.1 Introduction. 6.2 Serial memories. 6.3 Content-addressable memories (CAM). 6.4 Random-access memories (RAM). 6.5 Non-volatile memories. 6.6 Embedded memories. 6.7 Classification of the various memories. 6.8 Conclusions. 6.9 References. 6.10 Exercises. 7 Very Large Scale Integration (VLSI) and ASICs. 7.1 Introduction. 7.2 Digital ICs. 7.3 Abstraction levels for VLSI. 7.4 Digital VLSI design. 7.5 The use of ASICs. 7.6 Silicon realisation of VLSI and ASICs. 7.7 Conclusions. 7.8 References. 7.9 Exercises. 8 Low power, a hot topic in IC design. 8.1 Introduction. 8.2 Battery technology summary. 8.3 Sources of CMOS power consumption. 8.4 Technology options for low power. 8.5 Design options for power reduction. 8.6 Computing power versus chip power, a scaling perspective. 8.7 Conclusions. 8.8 References. 8.9 Exercises. 9 Robustness of nanometer CMOS designs: signal integrity, variability and reliability. 9.1 Introduction. 9.2 Clock generation, clock distribution and critical timing. 9.3 Signal integrity. 9.4 Variability. 9.5 Reliability. 9.6 Design organisation. 9.7 Conclusions. 9.8 References. 9.9 Exercises. 10 Testing, yield, packaging, debug and failure analysis. 10.1 Introduction. 10.2 Testing. 10.3 Yield. 10.4 Packaging. 10.5 Potential first silicon problems. 10.6 First-silicon debug and failure analysis. 10.7 Conclusions. 10.8 References. 10.9 Exercises. 11 Effects of scaling on MOS IC design and consequences for the roadmap. 11.1 Introduction. 11.2 Transistor scaling effects. 11.3 Interconnection scaling effects. 11.4 Scaling consequences for overall chip performance and robustness. 11.5 Potential limitations of the pace of scaling. 11.6 Conclusions. 11.7 References. 11.8 Exercises.
| Zusatzinfo | biography |
|---|---|
| Verlagsort | New York, NY |
| Sprache | englisch |
| Maße | 168 x 242 mm |
| Gewicht | 1407 g |
| Einbandart | gebunden |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 1-4020-8332-7 / 1402083327 |
| ISBN-13 | 978-1-4020-8332-7 / 9781402083327 |
| Zustand | Neuware |
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