VLSI Fault Modeling and Testing Techniques
Seiten
1993
Praeger Publishers Inc (Verlag)
978-0-89391-781-4 (ISBN)
Praeger Publishers Inc (Verlag)
978-0-89391-781-4 (ISBN)
This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models.
VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
brist /f George /i W.
Editor's Preface [vii]
1. Physical Fault Modeling and Simulation for VLSI MOS Circuits [1]
Mona E. Zaghloul
2. Designing CMOS Gates to Test Open Faults [32]
R. Rajsuman
3. Testing Bridging Faults in VLSI [58]
R. Rajsuman
4. Built-in Self-Test Techniques for Programmable Logic Arrays [90]
Chun-Yeh Liu and Kewal K. Saluja
5. Value Assignment Implication Constraints and Design for Testability [123]
Bijan Karimi and Louis G. Johnson
6. Testable Design Synthesis Methods [162]
Catherine H. Gebotys and Mohamed I. Elmasry
Author Index [195]
Subject Index [198]
| Erscheint lt. Verlag | 1.5.1993 |
|---|---|
| Sprache | englisch |
| Themenwelt | Informatik ► Grafik / Design ► Digitale Bildverarbeitung |
| Mathematik / Informatik ► Informatik ► Theorie / Studium | |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 0-89391-781-8 / 0893917818 |
| ISBN-13 | 978-0-89391-781-4 / 9780893917814 |
| Zustand | Neuware |
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