Advanced Digital Logic Design Using VHDL, State Machines, and Synthesis for FPGA's
CL Engineering (Verlag)
978-0-534-46602-2 (ISBN)
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Sunggu Lee received the B.S.E.E. degree with highest distinction from the University of Kansas, Lawrence, in 1985 and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1987 and 1990, respectively. He is currently an Associate Professor in the Department of Electronic and Electrical Engineering at the Pohang University of Science and Technology (POSTECH), Pohang, Korea. Prior to this appointment, he was an Assistant Professor in the Department of Electrical Engineering at the University of Delaware in Newark, Delaware, U.S.A. From June 1997 to June 1998, he spent one year as a Visiting Scientist at the IBM T. J. Watson Research Center. His research interests are in parallel computing using clusters, fault-tolerant computing, and real-time computing.
Preface
Chapter 1 Condensed Overview of Introductory Digital Logic Design
1.1Number Formats
1.2Combinational Logic
1.2.1Combinational Logic Devices
1.2.2Combinational Logic Circuit Design
1.3Sequential Logic
1.3.1Sequential Logic Devices
1.3.2Synchronous Sequential Circuit Design
1.3.3Hazards and Glitches
1.3.4Mestastability
Chapter 2Digital Logic Design Using Hardware Description Languages
2.1Hardware description Languages
2.2Design Flow
2.3Synthesis
2.4Register Transfer Level Notation
2.5Logic Simulation
2.6Properties of Actual Circuits
Chapter 3Introduction to VHDL and Test Benches
3.1Overview
3.2VHDL Basics
3.2.1Entity and Architecture
3.2.2Signals, Data, Types, Constants and Operators
3.2.3Libraries and Packages
3.2.4Structural and Behavioral
3.3Testing and the Test Bench
3.3.1Manufacturing Testing
3.3.2Functional Testing
3.3.3Test Benches
3.3.4VHDL Test Bench
3.4More Advanced VHDL Concepts
3.4.1Concurrent and Sequential VHDL
3.4.2Variables and Signals
3.4.3Delay Modeling
3.4.4Attributes
3.4.5Procedures and Functions
3.4.6Generics and Modeling a Bidirectional Bus
3.5Construction of Complete VHDL Programs
3.5.1Combinational Logic Circuits
3.5.2Sequential Logic Circuits
3.5.3Behavioral Modeling of More Complex Circuits
Chapter 4High-Level VHDL Coding for Synthesis
4.1Register Transfer Level Notation
4.2Combinational Logic Synthesis
4.2.1Using Concurrent Signal Assignment Statements for Combinational Logic
4.2.2Using Process Blocks for Combinational Logic
4.2.3Complex Combinational Logic Example
4.3Sequential Logic Synthesis
4.4Synthesis Heuristics
4.5Synthesis Using a Commercial Tool
4.6High-Level VHDL Coding
Chapter 5State Machine Design
5.1Manual State Machine Design
5.1.1Pseudocode
5.1.2RTL Program
5.1.3Datapath
5.1.4State Diagram
5.1.5Control Logic
5.1.6State Machine Design Using ASM Charts
5.2Automatic Synthesis-Based State Machine Design
5.2.1Automatic Synthesis-Based Design Procedure
5.2.2Algorithm to HDL Code Conversion
5.3Design Example: Vending Machine
5.3.1Automatic State Machine Design for a Vending Machine
5.3.2Manual State Machine Design for a Vending Machine
5.3.3Timing Diagram
5.3.4Correspondence Between Automatic and Manual Designs
5.4Design Example: LCD Controller
5.4.1Target LCD Module
5.4.2VHDL Solution
Chapter 6FPGA and Other Programmable Logic Devices
6.1Programmable Logic Devices
6.1.1Circuit Customization
6.1.2Programmable Logic Arrays
6.1.3Programmable Read Only Memories
6.1.4Programmable AND-Array Logic
6.2Field Programmable Gate Arrays
6.2.1Gate Arrays
6.2.2FPGA Overview
6.2.3Xilinx FPGA Example
6.2.4FPGA Configuration
6.2.5Xilinx Spartan-II FPGA Configuration Example
6.2.6Boundary Scan
Chapter 7Design of a USB Protocol Analyzer
7.1Overview of USB Full-Speed Mode
7.1.1Packet Transfer Protocol
7.1.2Initialization Sequence
7.1.3Physical Layer Interface
7.1.4USB Packets
7.1.5Cyclic Redundancy Checks
7.1.6Observation of Actual USB Signals
7.2Design Overview
7.2.1State Machine
7.2.2Subcircuit Partitioning
7.3VHDL Solution
7.3.1Digital Phase Locked Loop
7.3.2NRZI-to-Binary Converter
7.3.3CRC Checker Subcircuits
7.3.4Packet ID Recognizer
7.3.5State Machine Subcircuit
7.3.6Top-Level Circuit
7.3.7Test Bench Code for Entire Circuit
7.4Simulation Results
Chapter 8Design of Fast Arithmetic Units
8.1Adder Designs
8.1.1Ripple Carry adder
8.1.2Carry Lookahead Adder
8.1.3Carry Save Adder
8.2Multiplier Designs
8.2.1Combinational Multiplier
8.2.2Sequential Multiplier
8.2.3Fast Multiplication
8.2.4Multiply-Accumulate Units
8.3Pipelined Functional Units
8.3.1Introduction to Pipelining
8.3.2Pipelined Multiply-Accumulate Units
8.4HDL Implementations
8.4.1HDL Implementation Overview
8.4.2HDL Design for a Pipelined Multiply-Accumulate Unit
8.4.3Test Bench and Simulation Results
Chapter 9Design of a Pipelined RISC Microprocessor
9.1Introduction to Microprocessors
9.1.1Reduced Instruction Set Computers
9.1.2Basic Computer Operation
9.2The THUMB Microprocessor Architecture
9.2.1Thumb Programming Model
9.2.2Overview of the THUMB Instruction Set
9.3Instruction Pipeline Design
9.3.1Pipeline Hazards
9.3.2Hazard Prevention Techniques
9.3.3Pipeline Hazard Solutions Adopted
9.4HDL Implementation of the THUMB Pipeline
9.4.1VHDL THUMB Implementation
9.4.2Test Bench Based Verification
ATHUMB Instruction Set Listing
| Sprache | englisch |
|---|---|
| Maße | 192 x 240 mm |
| Gewicht | 940 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 0-534-46602-8 / 0534466028 |
| ISBN-13 | 978-0-534-46602-2 / 9780534466022 |
| Zustand | Neuware |
| Haben Sie eine Frage zum Produkt? |
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