Nicht aus der Schweiz? Besuchen Sie lehmanns.de
Verilog Digital System Design - Zainalabedin Navabi

Verilog Digital System Design

Buch | Hardcover
384 Seiten
2005 | 2nd edition
McGraw-Hill Professional (Verlag)
978-0-07-144564-1 (ISBN)
CHF 94,40 inkl. MwSt
  • Titel ist leider vergriffen;
    keine Neuauflage
  • Artikel merken
Shows electronics designers and students how to deploy Verilog in sophisticated digital systems design. This book includes worked examples for Verilog 2001, synthesis standards. It also provides coverage of the OVI verification library.
This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library.

Zainalabedin Navabi, Ph.D., navabi@ece.neu.edu, is adjunct professor of electrical and computer engineering at Northeastern University and the author of both editions of VDHL: Analysis and Modeling of Digital Systems, published by McGraw-Hill. Since 1981, Dr. Navabi has worked in the design, definition and implementation of hardware description languages and the synthesis and testing of digital systems. He has developed and supervised the development of many HDL-related software packages and tools, and has directed projects in VLSI design, test synthesis, simulation, synthesis, and other aspects of digital system automation. He has served as a consultant for several EDA companies developing HDL based tools and environments. Dr. Navabi is a member of ACM, IEEE, IEEE computer society, and an active participant in IEEE DASC committee that sets standards related to hardware description languages

Chapter 1: Design Automation with VerilogChapter 2: Register Transfer Level Design with VerilogChapter 3: Verilog Language ConceptsChapter 4: Combinational Circuit DescriptionChapter 5: Sequential Circuit DescriptionChapter 6: Component Test and VerificationChapter 7: Detailed Modeling Chapter 8: RT Level Design and TestAppendix A: List of KeywordsAppendix B: Frequently Used Sysytem Tasks and FunctionsAppendix C: Compiler DirectivesAppendix D: Verilog Formal Syntax DefinitionAppendix E: Verilog Assertion Monitors

Zusatzinfo Illustrations
Sprache englisch
Themenwelt Technik Elektrotechnik / Energietechnik
ISBN-10 0-07-144564-1 / 0071445641
ISBN-13 978-0-07-144564-1 / 9780071445641
Zustand Neuware
Haben Sie eine Frage zum Produkt?
Mehr entdecken
aus dem Bereich
Wegweiser für Elektrofachkräfte

von Gerhard Kiefer; Herbert Schmolke; Karsten Callondann

Buch | Hardcover (2024)
VDE VERLAG
CHF 67,20