Accelerating Network Functions Using Reconfigurable Hardware
Springer International Publishing (Verlag)
978-3-031-52871-2 (ISBN)
This book reports on new concepts and methods to design network functions on programmable hardware to accelerate connectivity. First, it introduces the host bypassing concept for improved integration of hardware accelerators in computer systems operating 5G radio access networks. This novel concept bypassed the system's main memory and established direct connectivity between the accelerator and network interface card. This concept leads to improved throughput and significantly lowered latency jitter compared to existing methods. Second, the book analyzes different programmable hardware technologies for hardware-accelerated Internet subscriber handling, including three P4-programmable platforms and FPGAs. It shows that all the approaches have excellent performance and are suitable for Internet access creation. In turn, it presents a fully-fledged accelerated User Plane Function (UPF) designed upon these concepts and its testing in an end-to-end 5G standalone network. Third, it analyses and demonstrates the usability of Active Queue Management (AQM) algorithms on programmable hardware as an expansion to the access edge. It shows the feasibility of the CoDel AQM algorithm and discusses the challenges and constraints to be considered when limited hardware is used, resulting in significant improvements in the Quality of Service. Furthermore, the P4STA measurement framework is introduced, a network function benchmarking concept combing precise hardware-based time measurement methods with software-based load generation to simultaneously ensure high measurement accuracy and flexibility. Researchers and professionals will find in this book new solutions to improve both fixed and mobile internet access networks, offering an informative and inspiring reading for researchers and professionals involved in building the next generation of access edge networks and underlying technology.
Introduction.- Background and State-of-the Art.- Design of QOS-Aware Network Functions.- P4sta: High precision network Function Benchmarking.- Evaluation.
| Erscheinungsdatum | 20.04.2024 |
|---|---|
| Reihe/Serie | Springer Theses |
| Zusatzinfo | XVI, 177 p. 78 illus., 72 illus. in color. |
| Verlagsort | Cham |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| Technik ► Nachrichtentechnik | |
| Schlagworte | Active Queue Management • Hierarchical Quality of Service (HQoS) • High Performance Packet Timestamping • Host Bypassing • Load Generation • Network Functions Acceleration • P4STA Framework • Programmable Data Plane Hardware |
| ISBN-10 | 3-031-52871-9 / 3031528719 |
| ISBN-13 | 978-3-031-52871-2 / 9783031528712 |
| Zustand | Neuware |
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