A Guide to VHDL
Seiten
1992
Kluwer Academic Publishers (Verlag)
978-0-7923-9255-2 (ISBN)
Kluwer Academic Publishers (Verlag)
978-0-7923-9255-2 (ISBN)
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Intended for the engineer who needs to develop, document, simulate and synthesize a design using the VHDL language, this is a guide for system and chip designers who are working with VHDL CAD tools and who have some experience programming in FORTRAN, PASCAL or C and have used a logic simulator.
"A Guide to VHDL" is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is a guide for system and chip designers who are working with VHDL CAD tools and who have some experience programming in FORTRAN, PASCAL or C and have used a logic simulator. The work includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapter can be run to reinforce the learning experience. For practical purposes, the book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. The guide can be used as a primer since its contents are appropriate for an introductory course in VHDL.
"A Guide to VHDL" is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is a guide for system and chip designers who are working with VHDL CAD tools and who have some experience programming in FORTRAN, PASCAL or C and have used a logic simulator. The work includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapter can be run to reinforce the learning experience. For practical purposes, the book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. The guide can be used as a primer since its contents are appropriate for an introductory course in VHDL.
VHDL designs; primitive elements 1+1 does not equal 2; sequential statements; advanced types; signals and signal assignments; concurrent statements; structural VHDL; packages and libraries; advanced topics; VHD: and logic synthesis; VHDL structure and syntax - reserved words, application examples.
| Zusatzinfo | bibliography, index |
|---|---|
| Sprache | englisch |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 0-7923-9255-8 / 0792392558 |
| ISBN-13 | 978-0-7923-9255-2 / 9780792392552 |
| Zustand | Neuware |
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