ESD
John Wiley & Sons Inc (Verlag)
978-1-118-95446-1 (ISBN)
ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies. New features in the 2nd edition:
Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs.
Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS.
Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications
Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-digitation, and common centroid techniques.
Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5.
Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges.
ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit & semiconductor engineers and quality, reliability &analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.
Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” Voldman was a member of the semiconductor development of IBM, Qimonda, and Intersil and worked as a full time consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) and a consultant on latchup, for the Samsung Electronics Corporation. He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally reaching over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, China and Senegal. He is a recipient of 252 issued US patents and has written over 150 technical papers. He has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents. Dr. Voldman is an author of the book series including ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design,, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of booksare also released.
About the Author xix
Preface xxi
Acknowledgments xxv
1 Electrostatic Discharge 1
1.1 Electricity and Electrostatic Discharge 1
1.1.1 Electricity and Electrostatics 1
1.1.2 Electrostatic Discharge 2
1.1.3 Key ESD Patents, Inventions, and Innovations 4
1.1.4 Table of ESD Defect Mechanisms 8
1.2 Fundamental Concepts of ESD Design 11
1.2.1 Concepts of ESD Design 12
1.2.2 Device Response to External Events 13
1.2.3 Alternate Current Loops 14
1.2.4 Switches 14
1.2.5 Decoupling of Current Paths 15
1.2.6 Decoupling of Feedback Loops 15
1.2.7 Decoupling of Power Rails 15
1.2.8 Local and Global Distribution 15
1.2.9 Usage of Parasitic Elements 16
1.2.10 Buffering 16
1.2.11 Ballasting 16
1.2.12 Unused Section of a Semiconductor Device, Circuit, or Chip Function 17
1.2.13 Impedance Matching between Floating and Nonfloating Networks 17
1.2.14 Unconnected Structures 17
1.2.15 Utilization of Dummy Structures and Dummy Circuits 17
1.2.16 Nonscalable Source Events 17
1.2.17 Area Efficiency 18
1.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 18
1.3.1 Esd 18
1.3.2 Electrical Overstress 19
1.3.3 Electromagnetic Interference 19
1.3.4 Electromagnetic Compatibility 19
1.3.5 Latchup 19
1.4 ESD Models 19
1.4.1 Human Body Model 20
1.4.2 Machine Model 21
1.4.3 Cassette Model (Small Charge Model) 24
1.4.4 Charged Device Model 24
1.4.5 Transmission Line Pulse 25
1.4.6 Very Fast Transmission Line Pulse 26
1.5 ESD and System-Level Test Models 28
1.5.1 IEC 61000-4-2 29
1.5.2 Human Metal Model 29
1.5.3 IEC 61000-4-5 30
1.5.4 Charged Board Model 31
1.5.5 Cable Discharge Event 32
1.5.5.1 CDE and Scaling 36
1.5.5.2 CDE—Cable Measurement Equipment 37
1.5.5.3 Cable Configuration—Test Configuration 38
1.5.5.4 Cable Configuration—Floating Cable 38
1.5.5.5 Cable Configuration—Held Cable 38
1.5.5.6 CDE—Peak Current versus Charged Voltage 39
1.5.5.7 CDE—Plateau Current versus Charged Voltage 39
1.6 Time Constants 39
1.6.1 Characteristic Times 39
1.6.2 Electrostatic and Magnetostatic Time Constants 39
1.6.2.1 Charge Relaxation Time 39
1.6.2.2 Magnetic Diffusion Time 40
1.6.2.3 Electromagnetic Wave Transit Time 40
1.6.3 Thermal Time Constants 42
1.6.3.1 Heat Capacity 42
1.6.3.2 Thermal Diffusion 42
1.6.3.3 Heat Transport Equation 42
1.6.4 Thermal Physics Time Constants 43
1.6.4.1 Adiabatic, Thermal Diffusion Timescale, and Steady State 44
1.6.5 Semiconductor Device Time Constants 45
1.6.5.1 Depletion Region Transit Time 45
1.6.5.2 Silicon Diode Storage Delay Time 45
1.6.5.3 Bipolar Base Transit Time 46
1.6.5.4 Bipolar Turn-on Transient Time 46
1.6.5.5 Bipolar Turn-off Transient Time 46
1.6.5.6 Bipolar Emitter Transition Capacitance Charging Time 46
1.6.5.7 Bipolar Collector Capacitance Charging Time 47
1.6.5.8 SCR Time Response 47
1.6.5.9 MOSFET Transit Time 47
1.6.5.10 MOSFET Drain Charging Time 48
1.6.5.11 MOSFET Gate Charging Time 48
1.6.5.12 MOSFET Parasitic Bipolar Response Time 48
1.6.6 Circuit Time Constants 49
1.6.6.1 Pad Capacitance 49
1.6.6.2 Half-Pass TGs 49
1.6.6.3 N-Channel Half-Pass Transistor Charging Time Constant 49
1.6.6.4 Half-pass Transistor TG Discharge Time Constant 49
1.6.6.5 P-Channel Half-Pass Transistor Charging Time Constant 49
1.6.6.6 Inverter Propagation Delay Time Constants 50
1.6.6.7 High-to-Low and Low-to-High Transition Time 50
1.6.6.8 Inverter Propagation Delay Time 51
1.6.6.9 Series N-channel MOSFETs Discharge Delay Time 51
1.6.6.10 Series P-channel MOSFETs Charge Delay Time 51
1.6.7 Chip-Level Time Constants 52
1.6.7.1 Peripheral I/O Power Bus Time Constant 52
1.6.7.2 Core Chip Time Constant 53
1.6.7.3 Substrate Time Constants 53
1.6.7.4 Package Time Constants 54
1.6.8 ESD Time Constants 54
1.6.8.1 ESD Events 55
1.6.8.2 HBM Characteristic Time 55
1.6.8.3 mm Characteristic Time 56
1.6.8.4 CDM Characteristic Time 57
1.6.8.5 Charged Cable Model Characteristic Time 57
1.6.8.6 CDE Model 57
1.6.8.7 CCM Characteristic Time 58
1.6.8.8 TLP Model Characteristic Time 58
1.6.8.9 VF-TLP Model Characteristic Time 59
1.7 Capacitance, Resistance, and Inductance and ESD 59
1.7.1 The Role of Capacitance 59
1.7.2 The Role of Resistance 60
1.7.3 The Role of Inductance 61
1.8 Rules of Thumb and ESD 62
1.8.1 ESD Design: An “ESD Ohm’s Law”—A Simple ESD Rule-of-Thumb Design Approach 62
1.9 ESD Scaling 63
1.10 Lumped versus Distributed Analysis and ESD 65
1.10.1 Current and Voltage Distributions 65
1.10.2 Lumped versus Distributed Systems 66
1.10.3 Distributed Systems—Ladder Network Analysis 67
1.10.4 RLC Distributed Systems 69
1.10.5 Resistor–Capacitor (RC) Distributed Systems 74
1.10.6 RG Distributed Systems 77
1.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 79
1.11.1 Chip Mean Pin Power-to-Failure 80
1.11.2 Chip Pin Standard Deviation Power-to-Failure 80
1.11.3 Chip Mean Pin Power-to-Failure to ESD Specification Margin 80
1.11.4 Worst-Case Pin Power-to-Failure to Specification ESD Margin 81
1.11.5 Total ESD Area to Total Chip Area Ratio 81
1.11.6 ESD Area to I/O Area Ratio 81
1.11.7 Circuit ESD Metrics 82
1.11.7.1 Circuit ESD Protection Level to ESD Loading Effect 82
1.11.7.2 Circuit Performance to ESD Loading Effect 82
1.11.7.3 ESD Area to Total Circuit Area Ratio 83
1.11.7.4 Circuit ESD Level to Specification Margin 83
1.11.7.5 Device ESD Metric 83
1.12 ESD Quality and Reliability Business Metrics 84
1.13 Twelve Steps to Building an ESD Strategy 85
1.14 Summary and Closing Comments 86
Problems 87
References 87
2 Design Synthesis 94
2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 94
2.2 Electrical and Spatial Connectivity 95
2.2.1 Electrical Connectivity 95
2.2.2 Thermal Connectivity 95
2.2.3 Spatial Connectivity 96
2.3 ESD, Latchup, and Noise 96
2.3.1 Noise 97
2.3.2 Latchup 98
2.4 Interface Circuits and ESD Elements 98
2.5 ESD Power Clamp Networks 101
2.5.1 Placement of ESD Power Clamps 104
2.6 ESD Rail-to-Rail Networks 105
2.6.1 Placement of ESD Rail-to-Rail Networks 107
2.6.2 Peripheral and Array I/O 107
2.7 Guard Rings 109
2.8 Pads, Floating Pads, and No-connect Pads 111
2.9 Structures under Bond Pads 112
2.10 Mixed Signal Architecture: CMOS 112
2.10.1 Digital and Analog CMOS Architecture 114
2.10.2 Digital and Analog Floor Plan: Placement of Analog Circuits 114
2.11 MS Architecture: Digital, Analog, and RF Architecture 116
2.12 Digital-to-Analog Interdomain Signal Line Failures 118
2.12.1 Digital-to-Analog Core Spatial Isolation 120
2.12.2 Digital-to-Analog Core Ground Coupling 120
2.12.3 Digital-to-Analog Core Resistive Ground Coupling 120
2.12.4 Digital-to-Analog Core Diode Ground Coupling 120
2.12.5 Domain-to-Domain Signal Line ESD Networks 122
2.12.6 Domain-to-Domain Third-Party Coupling Networks 122
2.12.7 Domain-to-Domain Cross-Domain ESD Power Clamp 123
2.13 Summary and Closing Comments 124
Problems 124
References 125
3 MOSFET ESD Design 129
3.1 Basic ESD Design Concepts 129
3.2 ESD MOSFET Design: Channel Length 136
3.2.1 Channel Length and Linewidth Control 136
3.2.2 ACLV Control 138
3.2.3 MOSFET ESD Design Practices 142
3.3 N-Channel MOSFET Design: Channel Width 143
3.4 ESD MOSFET Design: Contacts 144
3.4.1 Gate-to-Contact Spacing 144
3.4.1.1 Off-Axis Current Distribution 148
3.4.1.2 Self-Heating Equienergy Contours 148
3.4.2 Contact-to-Contact Space 149
3.4.3 ESD Design: End Contact 152
3.4.4 ESD MOSFET Design: Contacts to Isolation Edge 153
3.5 ESD MOSFET Design: Metal Distribution 153
3.5.1 MOSFET Metal Bus Design and Current Distribution 153
3.5.2 MOSFET Ladder Network Model 154
3.5.3 MOSFET Wiring: Parallel Current Distribution 158
3.5.4 MOSFET Wiring: Antiparallel Current Distribution 162
3.6 ESD MOSFET Design: Silicide Masking 165
3.6.1 ESD MOSFET Design: Silicide Mask Design 165
3.6.2 ESD MOSFET Design: Silicide Mask Design over Source and Drain 166
3.6.3 ESD MOSFET Design: Silicide Mask Design over Gate 167
3.7 ESD MOSFET Design: Series Cascode Configurations 170
3.7.1 MOSFET ESD Design: Series Cascode MOSFET 170
3.7.2 Integrated Cascoded MOSFETs 171
3.8 ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques 174
3.8.1 Grounded-Gate Resistor-Ballasted MOSFET 174
3.8.2 Soft Substrate Grounded-Gate Resistor-Ballasted MOSFET 176
3.8.3 Gate-Coupled Domino Resistor-Ballasted MOSFET 177
3.8.4 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with MOSFET 179
3.8.5 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 180
3.9 ESD MOSFET Design: Enclosed Drain Design Practice 181
3.10 ESD MOSFET Interconnect Ballasting Design 182
3.11 ESD MOSFET Design: Source and Drain Segmentation 184
3.12 MOSFET Design for Analog Applications 185
3.13 Summary and Closing Comments 187
Problems 187
References 188
4 ESD Design: Diode Design 191
4.1 ESD Diode Design: ESD Basics 191
4.1.1 Basic ESD Design Concepts 191
4.1.2 ESD Diode Design: ESD Diode Operation 193
4.2 ESD Diode Anode Design 194
4.2.1 P+ Diffusion Anode Width Effect 195
4.2.2 P+ Anode Contacts 195
4.2.3 P+ Anode Silicide to Edge Design 195
4.2.4 P+ Anode to N+ Cathode Isolation Spacing 198
4.2.5 P+ Anode Diode End Effects 198
4.2.6 Circular and Octagonal ESD Diode Design 200
4.3 ESD Diode Design: Interconnect Wiring 202
4.3.1 Parallel Wiring Design 203
4.3.2 Antiparallel Wiring Design 203
4.3.3 Quantized Tapered Parallel and Antiparallel Wiring 203
4.3.4 Continuous Tapered Antiparallel and Parallel Wiring 203
4.3.5 Perpendicular (and Broadside) Wiring with Center-Fed Design 205
4.3.6 Perpendicular (and Broadside) with Uniform Metal Width 206
4.3.7 Perpendicular (and Broadside) Wiring with T-Shaped Extensions 207
4.3.8 Metal Design for Structures under Bond Pads 208
4.4 ESD Design: Polysilicon-Bound Diode Designs 210
4.4.1 ESD Design Issues with Polysilicon-Bound Diode Structures 212
4.5 N-Well Diode Design 213
4.5.1 N-Well Diode Wiring Design 213
4.5.2 N-Well Contact Density 214
4.5.3 N-Well ESD Design, Guard Rings, and Adjacent Structures 214
4.6 N+/P Substrate Diode Design 216
4.7 ESD Design: Diode String Design 217
4.7.1 ESD Design: Diode String Design—Architecture 223
4.7.2 Diode String Elements in Multiple I/O Environments 223
4.7.3 Integration of Signal Pads 224
4.7.4 ESD Design: Diode String Design—Darlington Amplification 227
4.7.5 ESD Design: Diode String Design—Area Scaling 229
4.8 Triple-Well ESD Diode Design 231
4.9 Summary and Closing Comments 234
Problems 234
References 236
5 ESD Design: Passive Resistors 239
5.1 N-Well Resistors 239
5.1.1 N-Well ESD Design Issues 239
5.1.2 N-Well Resistors ESD Design Issues: Integration with MOSFETs 243
5.1.3 N-Well Resistor Ballasting Design 245
5.2 N-Diffusion Resistor Design 248
5.2.1 N-Diffusion Resistors for ESD Protection 248
5.2.2 N-Diffusion Resistors Ballasting Design 249
5.3 P-Diffusion Resistor Design 252
5.3.1 P-Diffusion Resistors for ESD Protection 253
5.4 Br 254
5.4.1 BR Design 254
5.4.2 BR as an ESD Diode Element 256
5.4.3 BR as an ESD HBM and CDM Element 257
5.4.4 BR Ballasting 260
5.4.5 BR Design Integration and ESD 261
5.4.6 BR: Current Robbing and Balancing ESD and Resistor Parasitics 263
5.4.7 BR-to-BR ESD Failure Mechanisms 266
5.4.8 BR Gate Connection and Failure Mechanisms 267
5.5 Summary and Closing Comments 268
Problems 268
References 270
6 Passives for Digital, Analog, and RF Applications 271
6.1 Analog Design Layout Revisited 271
6.1.1 Analog Design: Local Matching 272
6.1.2 Analog Design: Global Matching 272
6.1.3 Symmetry 273
6.1.4 Layout Design Symmetry 273
6.1.5 Thermal Symmetry 273
6.2 Common Centroid Design 274
6.2.1 Common Centroid Arrays 274
6.2.2 One-Axis Common Centroid Design 275
6.2.3 Two-Axis Common Centroid Design 275
6.3 Interdigitation Design 275
6.4 Common Centroid and Interdigitation Design 276
6.5 Passive Element Design 277
6.6 Resistor Element Design 277
6.6.1 Resistor Element Design: Dogbone Layout 277
6.6.2 Resistor Design: Analog Interdigitated Layout 278
6.6.3 Dummy Resistor Layout 278
6.6.4 Thermoelectric Cancellation Layout 279
6.6.5 Electrostatic Shield 280
6.6.6 Interdigitated Resistors and ESD Parasitics 281
6.7 Capacitor Element Design 283
6.8 Inductor Element Design 283
6.9 Summary and Closing Comments 286
Problems 286
References 286
7 Off-Chip Drivers and ESD 288
7.1 Off-chip Drivers 288
7.1.1 OCD I/O Standards and ESD 289
7.1.2 OCD ESD Design Basics 290
7.1.3 OCD: CMOS Asymmetric Pull-Up/Pull-Down 291
7.1.4 OCD: CMOS Symmetric Pull-Up/Pull-Down 292
7.1.5 OCD: Gunning Transceiver Logic 294
7.1.6 OCD: High-Speed Transceiver Logic 295
7.1.7 OCD: Stub Series-Terminated Logic 296
7.2 OCDs: mvi 297
7.3 OCDs: Self-Bias Well OCD Networks 297
7.3.1 Self-Bias Well OCD Networks 297
7.3.2 ESD Protection Networks for Self-Bias Well OCD Networks 300
7.4 Programmable Impedance OCD Network 302
7.4.1 OCD: PIMP OCD Networks 302
7.4.2 ESD Input Protection Networks for PIMP OCDs 305
7.5 OCDs: Universal OCDs 305
7.6 OCDs: Gate-Array OCD Design 306
7.6.1 Gate-Array OCD ESD Design Practices 306
7.6.2 Gate-Array OCD Design—Usage of Unused Elements 306
7.6.3 Gate-Array OCD Design—Impedance Matching of Unused Elements 307
7.6.4 OCD ESD Design—Power Rails Over Multifinger MOSFETs 308
7.7 OCDs: Gate-Modulated Networks 309
7.7.1 OCD: Gate-Modulated MOSFET ESD Network 309
7.7.2 OCD Simplified Gate-Modulated Network 310
7.8 OCDs ESD Design: Integration of Coupling and Ballasting Techniques 311
7.8.1 Ballasting and Coupling 311
7.8.2 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 311
7.8.3 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with an MOSFET 312
7.8.4 Gate-Coupled Domino Resistor-Ballasted MOSFET 314
7.9 Substrate-Modulated Resistor-Ballasted MOSFET 315
7.10 Summary and Closing Comments 317
Problems 318
References 319
8 Receiver Circuits 322
8.1 Receivers and ESD 322
8.1.1 Receivers and Receiver Delay Time 323
8.1.2 ESD Loading Effect on Receiver Performance 323
8.2 Receivers and ESD 324
8.2.1 Receivers and HBM 324
8.2.2 Receivers and CDM 325
8.3 Receivers and Receiver Evolution 327
8.3.1 Receiver Circuits with Half-Pass TG 327
8.3.2 Receiver with Full-Pass TG 330
8.3.3 Receiver, Half-Pass TG, and Keeper Network 332
8.3.4 Receiver, Half-Pass TG, and the Modified Keeper Network 335
8.4 Receiver Circuits with Pseudozero V T Half-Pass TG 337
8.5 Receiver with ZVT TG 339
8.6 Receiver Circuits with Bleed Transistors 342
8.7 Receiver Circuits with Test Functions 343
8.8 Receiver with Schmitt Trigger Feedback Network 344
8.9 Bipolar Transistor Receivers 347
8.9.1 Bipolar Single-Ended Receiver Circuits 347
8.10 Differential Receivers 349
8.10.1 Signal Differential Receiver 350
8.10.2 Signal CMOS Differential Receivers 350
8.10.3 Signal Bipolar Differential Receivers 350
8.11 CMOS Differential Receiver with Analog Layout Concepts 355
8.11.1 CMOS Differential Receiver Capacitance Loading 355
8.11.2 CMOS Differential Receiver ESD Mismatch 356
8.11.3 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout 359
8.11.4 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements 359
8.12 Summary and Closing Comments 363
Problems 364
References 366
9 Silicon on Insulator (SOI) ESD Design 368
9.1 Silicon on Insulator ESD Design Concepts 368
9.2 SOI Design MOSFET with Body Contact: T-Shape Layout Style 372
9.3 SOI Lateral Diode Structure 375
9.3.1 Transistors: Bulk Versus SOI Technology 375
9.3.2 SOI Lateral Diode Design 376
9.3.3 SOI Lateral Diode Perimeter Design 376
9.3.4 SOI Lateral Diode Channel Length Design 377
9.3.5 SOI Lateral P+/N−/N+ Diode Structure 377
9.3.6 SOI Lateral P+/P−/N+ Diode Structure 377
9.3.7 SOI Lateral P+/P−/N−/N+ Diode Structure 378
9.3.8 SOI Lateral Ungated P+/P−/N−/N+ Diode Structure 379
9.3.9 SOI Lateral Diode Structures and SOI MOSFET Halos 379
9.4 SOI BR Elements 380
9.5 Dynamic Threshold SOI MOSFET 381
9.6 SOI Dual-Gate MOSFET 384
9.7 SOI ESD Design: Mixed Voltage T-Shape Layout Style 384
9.8 SOI ESD Design: Mixed Voltage Diode Strings 384
9.9 SOI ESD Design: Double-Diode Network 385
9.10 Bulk to SOI ESD Design Remapping 387
9.11 SOI ESD Design in MVI Environments 391
9.12 Comparison of Bulk to SOI ESD Results 393
9.13 SOI ESD Design with Aluminum Interconnects 394
9.14 SOI ESD Design with Copper Interconnects 395
9.15 SOI ESD Design with Gate Circuitry 397
9.16 SOI FinFET Structure 399
9.17 Summary and Closing Comments 403
Problems 403
References 405
10 ESD Circuits: BiCMOS 408
10.1 Bipolar ESD Input Circuits 408
10.2 Diode-Configured Bipolar ESD Input Circuits 412
10.3 Bipolar ESD Input Circuits: Voltage-Triggered Elements 413
10.3.1 Voltage Triggered Bipolar ESD Input Circuits Classifications 413
10.3.2 Bipolar ESD Input: Resistor Grounded-Base ESD Input 414
10.3.3 Bipolar ESD Input Circuits: Zener Breakdown Voltage Triggered 418
10.3.4 Bipolar ESD: BV CEO Voltage-Triggered ESD Input 423
10.3.5 Bipolar ESD Input Circuits: Ultralow-Voltage Forward-Biased Voltage Trigger 430
10.3.6 ESD Bipolar Input Circuits: Future Networks and Scaling 433
10.3.7 Bipolar ESD Input Device Scaling 436
10.4 BiCMOS Mixed Signal Designs 437
10.5 Summary and Closing Comments 437
Problems 437
References 438
11 ESD Power Clamps 442
11.1 ESD Power Clamp Design Practices 442
11.1.1 Classification of ESD Power Clamps 444
11.1.2 Design Synthesis of ESD Power Clamp: Key Design Parameters 446
11.2 Design Synthesis of ESD Power Clamps Trigger Networks 446
11.2.1 Transient Response Frequency Trigger Element and the ESD Frequency Window 446
11.2.2 The ESD Power Clamp Frequency Design Window 447
11.2.3 Design Synthesis of ESD Power Clamp: Voltage-Triggered ESD Trigger Elements 447
11.3 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 449
11.3.1 ESD Power Clamp Trigger Condition versus Shunt Failure 450
11.3.2 ESD Clamp Element: Width Scaling 450
11.3.3 ESD Clamp Element: On-Resistance 451
11.3.4 ESD Clamp Element: Safe Operating Area 451
11.4 ESD Power Clamp Issues 452
11.4.1 ESD Power Clamp Issues: Power-Up and Power-Down 452
11.4.2 ESD Power Clamp Issues: False Triggering 452
11.4.3 ESD Power Clamp Issues: Precharging 452
11.4.4 ESD Power Clamp Issues: Postcharging 453
11.5 ESD Power Clamp Design 453
11.5.1 Native Power Supply RC-Triggered MOSFET ESD Power Clamp 453
11.5.2 Nonnative Power Supply RC-Triggered MOSFET ESD Power Clamp 454
11.5.3 ESD Power Clamp Networks with Improved Inverter Stage Feedback 454
11.5.4 ESD Power Clamp Design Synthesis: Forward-Bias-Triggered ESD Power Clamps 456
11.5.5 ESD Power Clamp Design Synthesis: IEC 61000-4-2 Responsive ESD Power Clamps 457
11.5.6 ESD Power Clamp Design Synthesis: Precharging and Postcharging Insensitive ESD Power Clamps 457
11.6 Master/Slave ESD Power Clamp Systems 458
11.7 Series-Stacked RC-Triggered ESD Power Clamps 460
11.8 ESD Power Clamps: Triple-Well Series Diodes as Core Clamps 460
11.9 Summary and Closing Comments 464
Problems 465
References 466
12 Bipolar ESD Power Clamps 468
12.1 Bipolar ESD Power Clamps 468
12.2 Bipolar Voltage-Triggered ESD Power Clamps 468
12.2.1 Bipolar ESD Power Clamp: Zener Breakdown Voltage Triggered 469
12.2.2 Bipolar ESD Power Clamp: BV CEO Voltage-Triggered ESD Power Clamp 470
12.3 ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps 473
12.4 Mixed Voltage Interface Forward-Bias Voltage and BV CEO Breakdown Synthesized Bipolar ESD Power Clamps 476
12.5 Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp 480
12.6 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered 485
12.7 Summary and Closing Comments 485
Problems 486
References 487
13 Silicon-Controlled Rectifier Power Clamps 489
13.1 ESD Silicon-Controlled Rectifier Circuits 489
13.1.1 Unidirectional SCR 489
13.1.2 Bidirectional SCR ESD Power Clamps 489
13.1.3 Medium-Level SCR ESD Power Clamps 490
13.1.4 Low Voltage Triggered SCR ESD Power Clamps 490
13.2 Lateral Diffused MOS Circuits 492
13.2.1 LOCOS-Defined LDMOS 492
13.2.2 Shallow Trench Isolation-Defined LDMOS 493
13.2.3 STI-Defined Isolated LDMOS 494
13.3 DeMOS Circuits 496
13.3.1 DeNMOS 497
13.3.2 DeNMOS-SCR Transistor 497
13.4 Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits 497
13.4.1 Uhv-ldmos 497
13.4.2 Uhv-ldmos-scr 497
13.5 Summary and Closing Comments 501
Problems 501
References 501
Glossary of Terms 504
Standards 509
Index 512
| Verlagsort | New York |
|---|---|
| Sprache | englisch |
| Maße | 178 x 252 mm |
| Gewicht | 980 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| Technik ► Nachrichtentechnik | |
| ISBN-10 | 1-118-95446-7 / 1118954467 |
| ISBN-13 | 978-1-118-95446-1 / 9781118954461 |
| Zustand | Neuware |
| Haben Sie eine Frage zum Produkt? |
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