Ultra Low Power Electronics and Adiabatic Solutions
ISTE Ltd and John Wiley & Sons Inc (Verlag)
978-1-84821-738-6 (ISBN)
Mechanisms of energy dissipation, the physical foundations for understanding CMOS components and sophisticated optimization techniques are explored in the first half of the book, before an introduction to reversible and quantum computing. Adiabatic computing and nano-relay technology are then explored as new solutions to achieving improvements in heat creation and energy consumption, particularly in renewed consideration of circuit architecture and component technology.
Concepts inspired by recent research into energy efficiency are brought together in this book, providing an introduction to new approaches and technologies which are required to keep pace with the rapid evolution of electronics.
Hervé Fanet is a Senior Scientist at CEA-LETI in France.
Introduction ix
Chapter 1. Dissipation Sources in Electronic Circuits 1
1.1. Brief description of logic types 1
1.1.1. Boolean logic 1
1.1.2. Combinational and sequential logic 7
1.1.3. NMOS and PMOS transistors 15
1.1.4. Complementary CMOS logic 21
1.1.5. Pass-transistor logic 26
1.1.6. Dynamic logic 29
1.2. Origins of heat dissipation in circuits 32
1.2.1. Joule effect in circuits 32
1.2.2. Calculating dynamic power 34
1.2.3. Calculating static power and its origins 37
Chapter 2. Thermodynamics and Information Theory 39
2.1. Recalling the basics: entropy and information 39
2.1.1. Statistical definition of entropy 39
2.1.2. Macroscopic energy and entropy 42
2.1.3. Thermostat exchange, Boltzmann’s law and the equal division of energy 46
2.1.4. Summary and example of energy production in a conductor carrying a current 50
2.1.5. Information and the associated entropy 52
2.2. Presenting Landauer’s principle 57
2.2.1. Presenting Landauer’s principle and other examples 57
2.2.2. Experimental validations of Landauer’s principle 64
2.3. Adiabaticity and reversibility 66
2.3.1. Adiabatic principle of charging capacitors 66
2.3.2. Adiabaticity and reversibility: a circuit approach 82
Chapter 3. Transistor Models in CMOS Technology 91
3.1. Reminder on semiconductor properties 91
3.1.1. State densities and semiconductor properties 91
3.1.2. Currents in a semiconductor 100
3.1.3. Contact potentials 102
3.1.4. Metal-oxide semiconductor structure 103
3.1.5. Weak and strong inversion 109
3.2. Long- and short-channel static models 114
3.2.1. Basic principle and brief history of semiconductor technology 114
3.2.2. Transistor architecture and Fermi pseudo-potentials 117
3.2.3. Calculating the current in a long-channel static regime 120
3.2.4. Calculating the current in a short-channel regime 129
3.3. Dynamic transistor models 132
3.3.1. Quasi-static regime 132
3.3.2. Dynamic regime 135
3.3.3. “Small signals” transistor model 136
Chapter 4. Practical and Theoretical Limits of CMOS Technology 143
4.1. Speed–dissipation trade-off and limits of CMOS technology 143
4.1.1. From the transistor to the integrated circuit 143
4.1.2. Trade-off between speed and consumption 146
4.1.3. The trade-off between dynamic consumption and static consumption 149
4.2. Sub-threshold regimes 154
4.2.1. Recall of the weak inversion properties 154
4.2.2. Limits to sub-threshold CMOS technology 160
4.3. Practical and theoretical limits in CMOS technology 162
4.3.1. Economic considerations and evolving methodologies 162
4.3.2. Technological difficulties: dissipation, variability and interconnects 164
4.3.3. Theoretical limits and open questions 171
Chapter 5. Very Low Consumption at System Level 177
5.1. The evolution of power management technologies 177
5.1.1. Basic techniques for reducing dynamic power 177
5.1.2. Basic techniques for reducing static power 180
5.1.3. Designing in 90, 65 and 45 nm technology 185
5.2. Sub-threshold integrated circuits 186
5.2.1. Sub-threshold circuit features 186
5.2.2. Pipeline and parallelization 187
5.2.3. New SRAM structures 187
5.3. Near-threshold circuits 188
5.3.1. Optimization method 189
5.4. Chip interconnect and networks 194
5.4.1. Dissipation in the interconnect 194
5.4.2. Techniques for reducing dissipation in the interconnect 199
Chapter 6. Reversible Computing and Quantum Computing 203
6.1. The basis for reversible computing 203
6.1.1. Introduction 203
6.1.2. Group structure of reversible gates 205
6.1.3. Conservative gates, linearity and affinity 206
6.1.4. Exchange gates 207
6.1.5. Control gates 210
6.1.6. Two basic theorems: “no fan-out” and “no cloning” 213
6.2. A few elements for synthesizing a function 214
6.2.1. The problem and constraints on synthesis 214
6.2.2. Synthesizing a reversible function 215
6.2.3. Synthesizing an irreversible function 218
6.2.4. The adder example 219
6.2.5. Hardware implementation of reversible gates 222
6.3. Reversible computing and quantum computing 225
6.3.1. Principles of quantum computing 226
6.3.2. Entanglement 227
6.3.3. A few examples of quantum gates 229
6.3.4. The example of Grover’s algorithm 231
Chapter 7. Quasi-adiabatic CMOS Circuits 237
7.1. Adiabatic logic gates in CMOS 237
7.1.1. Implementing the principles of optimal charge and adiabatic pipeline 237
7.1.2. ECRL and PFAL in CMOS 244
7.1.3. Comparison to other gate technologies 250
7.2. Calculation of dissipation in an adiabatic circuit 251
7.2.1. Calculation in the normal regime 251
7.2.2. Calculation in sub-threshold regimes 259
7.3. Energy-recovery supplies and their contribution to dissipation 264
7.3.1. Capacitor-based supply 264
7.3.2. Inductance-based supply 273
7.4. Adiabatic arithmetic architecture 280
7.4.1. Basic principles 280
7.4.2. Adder example 281
7.4.3. The interest in complex gates 283
Chapter 8. Micro-relay Based Technology 285
8.1. The physics of micro-relays 285
8.1.1. Different computing technologies 285
8.1.2. Different actuation technologies 287
8.1.3. Dynamic modeling of microelectro-mechanical relays 290
8.1.4. Implementation examples and technological difficulties 297
8.2. Calculation of dissipation in a micro-relay based circuit 299
8.2.1. Optimization of micro-relays through electrostatic actuation 299
8.2.2. Adiabatic regime solutions 307
8.2.3. Comparison between CMOS logic and micro-relays 312
Bibliography 317
Index 321
| Verlagsort | London |
|---|---|
| Sprache | englisch |
| Maße | 165 x 241 mm |
| Gewicht | 662 g |
| Themenwelt | Informatik ► Theorie / Studium ► Algorithmen |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 1-84821-738-2 / 1848217382 |
| ISBN-13 | 978-1-84821-738-6 / 9781848217386 |
| Zustand | Neuware |
| Haben Sie eine Frage zum Produkt? |
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