Nicht aus der Schweiz? Besuchen Sie lehmanns.de
Timing Verification of Application-Specific Integrated Circuits (ASICs) - Farzad Nekoogar

Timing Verification of Application-Specific Integrated Circuits (ASICs)

(Autor)

Buch | Hardcover
208 Seiten
1999
Prentice Hall (Verlag)
978-0-13-794348-7 (ISBN)
CHF 109,20 inkl. MwSt
  • Titel ist leider vergriffen;
    keine Neuauflage
  • Artikel merken
PLEASE PROVIDE COURSE INFORMATION

PLEASE PROVIDE
79434-7 It's About Time In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include: * Clock definitions, multicycle paths, false paths, and phase-locked loops * Behavioral and structural RTL coding for timing * Timing analysis of FPGAs * Pre and Post layout timing analysis * Synthesis and Timing constraints * EDA timing tools Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.

FARZAD NEKOOGAR, formerly a Technical Manager at Intrinsix Corp., has extensive practical experience verifying timing of ASICs, FPGAs, and systems-on-a-chip. He is a lecturer at the University of California at Davis, and is the author of "Digital Control Using Digital Signal Processing, " published by Prentice Hall PTR.

1. Introduction to Timing Verification.


Introduction. Overview of Timing Verification. Interface Timing Analysis.



2. Elements of Timing Verification.


Introduction. Clock Definitions. More on STA. Timing Analysis of Phase-Locked Loops.



3. Timing in ASICs.


Introduction. Prelayout Timing. Postlayout Timing. ASIC Sign-Off Checklist.



4. Programmable Logic Based Design.


Introduction. Programmable Logic Structures. Design Flow. Timing Parameters. Timing Analysis. HDL Synthesis. Software Development Systems.



A. PrimeTime.


B. Pearl.


C. TimingDesigner.


D. Transistor-Level Timing Verification.


References.


Index.


About the Author

Erscheint lt. Verlag 26.7.1999
Verlagsort Upper Saddle River
Sprache englisch
Maße 243 x 184 mm
Gewicht 336 g
Themenwelt Technik Elektrotechnik / Energietechnik
ISBN-10 0-13-794348-2 / 0137943482
ISBN-13 978-0-13-794348-7 / 9780137943487
Zustand Neuware
Haben Sie eine Frage zum Produkt?
Mehr entdecken
aus dem Bereich
Wegweiser für Elektrofachkräfte

von Gerhard Kiefer; Herbert Schmolke; Karsten Callondann

Buch | Hardcover (2024)
VDE VERLAG
CHF 67,20

von Jan Luiken ter Haseborg; Christian Schuster; Manfred Kasper

Buch | Hardcover (2023)
Carl Hanser (Verlag)
CHF 48,95