Network Processor Design (eBook)

Issues and Practices

PATRICK CROWLEY, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk (Autoren)

eBook Download: PDF

2002 | 1. Auflage
338 Seiten
Elsevier Science (Verlag)
978-0-08-051249-5 (ISBN)

Infos

As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. Network Processor Design: Issues and Practices is an essential reference on network processors for graduate students, researchers, and practicing designers.* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University. * Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.

Mark A. Franklin received his B.A., B.S.E.E. and M.S.E.E. from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently at Washington University in St. Louis where he has a joint appointment in Electrical Engineering and Computer Science, and holds the Urbauer Chair in Engineering. He founded and is Director of the Computer and Communications Research Center and until recently was the Director of the Undergraduate Program in Computer Engineering. Dr. Franklin is engaged in research, teaching and consulting in the areas of computer and communications architectures, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation. He is a Fellow of the IEEE, a member of the ACM, and has been an organizer and reviewer for numerous professional conferences including the HPCA8 Workshop on Network Processors (2002). He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chairman of the ACM SIGARCH (Special Interest Group on Computer Architecture).

Inhalt

Front Cover 1
Network Processor Design Issues and Practices 2
Copyright Page 5
Contents 6
Preface 14
Chapter 1. Network Processors: An Introduction to Design Issues 16
1.1 Design Challenges 18
1.2 Design Techniques 19
1.3 Challenges and Conclusions 22
PART I: DESIGN PRINCIPLES 24
Chapter 2. Benchmarking Network Processors 26
2.1 Benchmarking Framework Overview 27
2.2 Hardware-Level Benchmarks 30
2.3 Microlevel Benchmarks 33
2.4 Function-Level Benchmarks 36
2.5 Related Work 38
References 39
Chapter 3. A Methodology and Simulator for the Study of Network Processors 42
3.1 Previous Work 43
3.2 Component Network Simulator (ComNetSim) 45
3.3 The Cisco Toaster2 47
3.4 Implementation of ComNetSim 50
3.5 Application Development 59
3.6 Organization and Configuration 63
3.7 Experiments and Results 63
3.8 Conclusion and Future Work 67
References 68
Chapter 4. Design Space Exploration of Network Processor Architectures 70
4.1 Models for Streams, Tasks, and Resources 73
4.2 Analysis Using a Scheduling Network 78
4.3 Multiobjective Design Space Exploration 94
4.4 Case Study 96
Acknowledgments 101
References 102
Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing 106
5.1 Bit-Level Data Flow Analysis and Bit Value Inference 110
5.2 Code Selection 114
5.3 Register Allocation Considering Register Arrays 121
5.4 Dead Code Elimination 124
5.5 Implementation 125
5.6 Results 127
Acknowledgments 128
References 128
Chapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization 132
6.1 The Performance Model 134
6.2 Workload and System Characteristics 141
6.3 Design Results 145
6.4 Conclusion 153
References 153
Chapter 7. A Benchmarking Methodology for Network Processors 156
7.1 Related Work 158
7.2 A Benchmarking Methodology 161
7.3 The Benchmark Suite 173
7.4 Preliminary Results 175
7.5 Conclusion and Future Work 178
References 179
Chapter 8. A Modeling Framework for Network Processor Systems 182
8.1 Framework Description 183
8.2 System Modeling 192
8.3 IPSec VPN Decryption 199
8 .4 Packet Size Distributions 201
8.5 Conclusion and Future Work 202
Acknowledgments 202
References 202
PART II: PRACTICES 204
Chapter 9. An Industry Analyst's Perspective on Networ k Processors 206
9.1 History of Packet Processing 206
9.2 The Need for Programmability 214
9.3 Network Processors 218
9.4 Where Do NPs Fit in a System? 220
9.5 Evaluating NP Solutions 224
9.6 Trends 230
Chapter 10. Agere Systems—Communications Optimized PayloadPlus Network Processor Architecture 234
10.1 Target Applications 235
10.2 PayloadPlus Optimized Pipeline-Based Hardware Architecture 235
10.3 3G/Media Gateway Application Example 240
10.4 FPP Details 240
10.5 RSP details 243
10.6 Software Architecture and Overview 245
10.7 Agere Performance Benefits at OC-48c 247
References 248
Chapter 11. Cisco Systems— Toaster 2 250
11.1 Target Application(s) 250
11.2 Packet Flow Example for a Centralized System 253
11.3 Packet Flow Example for a Distributed System 254
11.4 Toaster2 Hardware Architecture 255
11.5 External Memory Controller 256
11.6 Internal Column Memory 256
11.7 Input and Output Header Buffers 256
11.8 Toaster MicroController 257
11.9 Tag Buffer 260
11.10 Route Processor interface 260
11.11 Lock Controller 260
11.12 Software Architecture 261
11.13 Toaster Development Methodology and Environment 261
11.14 Performance Claims 262
11.15 Family of Toaster Network Processors 263
11.16 Conclusion 263
Chapter 12. IBM—PowerNP Network Processor 264
12.1 Hardware Architecture 266
12.2 Software 270
12.3 Performance 272
12.4 Conclusion 273
Acknowledgments 273
References 273
Chapter 13. Intel Corporation—Intel IXP2400 Network Processor: A Second-Generation Intel NPU 274
13.1 Target Applications 274
13.2 Hardware Architecture 275
13.3 Software Development Environment 281
13.4 IXP2400 System Configurations and Performance Analysis 288
13.5 CONCLUSION 289
References 290
Chapter 14. Motorola—C-5e Network Processor 292
14.1 Target Applications 293
14.2 Hardware Architecture 295
14.3 Software Architecture 302
14.4 Conclusion 305
References 305
Chapter 15. PMC-Sierra, Inc.— ClassiPI 306
15.1 Target Applications 306
15.2 ClassiPl Architecture 309
15.3 System Interface (SI) 310
15.4 Field Extraction Engine (FEE) 310
15.5 Classification Engine (CE) 310
15.6 External RAM (ERAM) Interface 312
15.7 ClassiPI Control and Sequencer Block 312
15.8 Cascade Interface 313
15.9 ClassiPI Implementation 314
15.10 Software Architecture and Development Kit 314
15.11 Platforms 314
15.12 Modules 315
15.13 Software Development 315
15.14 Simulator 316
15.15 Debugger 316
15.16 ClassiPl Application Example : A Complex Security-Enabled Router 317
15.17 Performance 319
15.18 Conclusion 319
References 320
Chapter 16. TranSwitch—ASPEN: Flexible Network Processing for Access Solutions 322
16.1 Applications 322
16.2 ASPEN Operation and Architecture 325
16.3 Programming Environment 331
16.4 Conclusion 332
References 333
Index 334
About the Editors 352

Produkt-Details

• Erscheint lt. Verlag: 16.10.2002
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Netzwerke
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Informatik ► Weitere Themen ► Hardware
• Themenwelt: Technik ► Fahrzeugbau / Schiffbau
• Themenwelt: Technik ► Luft- / Raumfahrttechnik
• ISBN-10: 0-08-051249-6 / 0080512496
• ISBN-13: 978-0-08-051249-5 / 9780080512495