Unleash the System On Chip using FPGAs and Handel C (eBook)

Rajanish K. Kamat, Santosh A. Shinde, Vinod G Shelake (Autoren)

eBook Download: PDF

2009 | 2009
XXIV, 174 Seiten
Springer Netherland (Verlag)
978-1-4020-9362-3 (ISBN)

Infos

With the rapid advances in technology, the conventional academic and research departments of Electronics engineering, Electrical Engineering, Computer Science, Instrumentation Engineering over the globe are forced to come together and update their curriculum with few common interdisciplinary courses in order to come out with the engineers and researchers with muli-dimensional capabilities. The gr- ing perception of the 'Hardware becoming Soft' and 'Software becoming Hard' with the emergence of the FPGAs has made its impact on both the hardware and software professionals to change their mindset of working in narrow domains. An interdisciplinary field where 'Hardware meets the Software' for undertaking se- ingly unfeasible tasks is System on Chip (SoC) which has become the basic pl- form of modern electronic appliances. If it wasn't for SoCs, we wouldn't be driving our car with foresight of the traffic congestion before hand using GPS. Without the omnipresence of the SoCs in our every walks of life, the society is wouldn't have evidenced the rich benefits of the convergence of the technologies such as audio, video, mobile, IPTV just to name a few. The growing expectations of the consumers have placed the field of SoC design at the heart of at variance trends. On one hand there are challenges owing to design complexities with the emergence of the new processors, RTOS, software protocol stacks, buses, while the brutal forces of deep submicron effects such as crosstalk, electromigration, timing closures are challe- ing the design metrics.

Inhalt

Preface. Foreword. Acknowledgements.
Chapter 1: Introduction1.1 Prologue1.2 Exceptional Attributes of the  SoC Technology1.3 Classical taxonomy: a holistic perspective extended towards  Integrated Circuits Classification1.4 System on Chip (SoC) Term and Scope1.5 Constituents of SoC1.6 Sprawling Growth of SoC market1.7 Choosing the platform, ASIC Vs FPGAs1.8 FPGA based Programmable SoC1.9 Orientation of the Book
Chapter 2: Familiarizing with Handel C2.1 EDA Tools i.e. Computer Aids for VLSI Design2.2 Background of Hardware Description Languages2.3 Expressing abstraction at higher levels2.4 Where C stands amidst the well established HDLs?2.5 Introducing Handel C 2.6 Top Down or Bottom up?2.7 Handel C: A boon for Software Professionals2.8 Handel C vs ANSI C2.9 Handel C Design Flow
Chapter 3: Sequential logic Design3.1 Design Philosophy of Sequential Logic3.2 D flip-flop3.3 Latch3.4 Realization of JK Flip-Flop3.5 Cell of  Hex counter for Counter Applications3.6 Realization of Shift Register for SoC3.7 LFSR Core for Security Applications in SoC3.8 Clock Scaling and Delay Generation in SoC3.9 SoC Data Queuing using FIFO3.10 Implementation of Stack though LIFO3.11 Soft IP core for Hamming Code
Chapter 4: Combinational Logic Design4.1 Introduction4.2 Design Metrics for the Combinational Logic Circuits: SoC Perspective4.3 Core of “2 to 4 decoder”4.4 “3 to 8 decoder” using hierarchical approach4.5 Priority Encoder 4 to 24.6 Soft IP Core of “7 to 3 encoder” Implementation4.7 IP core of ‘Parity generator’ for Communication Applications4.8 IP Core for Parity checker and error detection for Internet Protocol4.9 BCD TO Seven Segment converter4.10 Core of Binary to Gray Converter and Applications4.11 Realization of IP Core of Gray to Binary Converter4.12  Designing Barrel Shifters
Chapter 5: Arithmetic core design and Design Reuse of  Soft IP Cores5.1 Design Reuse Philosophy5.2 Advantages of on chip arithmetic5.3 Designing Half adder in Handel C 5.4 Full Adder 5.5 Ripple Carry Adder 5.6 Booth Algorithm and its realization on FPGA5.7 Building ALU in Handel C5.7 Third Party Tool Interface with Handel C5.8 Xilinx EDK Interface with Cores developed through Handel C
Chapter 6: Rapid Prototyping of the Soft IP cores on FPGA6.1 Prototyping Philosophy6.2 Rapid Design of Fuzzy Controller using Handel C6.3 Packet Processor Core for Inculcating Embedded Network Security using Mixed Design Flow6.4. A Linear Congruential Generator (LCG) SoC6.5 Implementation of Reusable Soft IP core of Blowfish Cipher
Chapter 7: Soft Processor Core for Accelerated Embedded Design7.1 Building SoC for temperature control application using Picoblaze7.2 Hardware Software Codesign of SoC with built in Position Algorithm
References. List of Tables. List of Figures. List of Programs.

Produkt-Details

• Erscheint lt. Verlag: 5.3.2009
• Zusatzinfo: XXIV, 174 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: FPGA • Fuzzy Controller • Handel C • Integrated circuit • Network on Chip (NoC) • Soft IP cores • System on chip (SoC)
• ISBN-10: 1-4020-9362-4 / 1402093624
• ISBN-13: 978-1-4020-9362-3 / 9781402093623