On Reducing Glitch Power in Combinational Circuits

Lei Wang (Autor)

Buch | Hardcover

133 Seiten

2011
Dr. Hut (Verlag)
978-3-8439-0093-5 (ISBN)

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In this thesis, first of all, a theoretical framework for dynamic power estimation is presented, in which the concepts of the conventional probabilistic simulation are extended. To cope with the modeling of temporal correlation, an exact glitch-filtering scheme using multidimensional signal probability is proposed within this framework. To compromise the runtime complexity, the exact glitch-filtering scheme is modified. Despite using the modified glitch-filtering scheme, the extended probabilistic simulation is still too slow to be applied to iterative power optimization. To get around time-consuming power estimation, power metric and its calculation method are introduced in this thesis. Based on the power metric, a heuristic gate sizing algorithm for glitch power reduction is proposed. By dividing the search strategy of the proposed gate sizing heuristic into an LP-based global search and a monotonic local search, the basic algorithm can be accelerated by more than 30% for cell-rich standard cell libraries. In addition, three multi-Vt assignment algorithms cooperating with gate sizing are also investigated.

Reihe/Serie	Elektronik
Maße	148 x 210 mm
Gewicht	305 g
Einbandart	gebunden
Themenwelt	Technik ► Elektrotechnik / Energietechnik
ISBN-10	3-8439-0093-0 / 3843900930
ISBN-13	978-3-8439-0093-5 / 9783843900935
Zustand	Neuware