High k Gate Dielectrics

Buch | Softcover

614 Seiten

2020
CRC Press (Verlag)
978-0-367-45444-9 (ISBN)

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The drive toward smaller and smaller electronic componentry of microelectronics is demanding new materials with higher electrical permittivity. An impressive collection of methods with in-depth coverage, High k Gate Dielectrics reviews the state-of-the-art in high permittivity gate dielectric research. Leading researchers from Europe and the USA de

The drive toward smaller and smaller electronic componentry has huge implications for the materials currently being used. As quantum mechanical effects begin to dominate, conventional materials will be unable to function at scales much smaller than those in current use. For this reason, new materials with higher electrical permittivity will be required, making this is a subject of intensive research activity within the microelectronics community.

High k Gate Dielectrics reviews the state-of-the-art in high permittivity gate dielectric research. Consisting of contributions from leading researchers from Europe and the USA, the book first describes the various deposition techniques used for construction of layers at these dimensions. It then considers characterization techniques of the physical, chemical, structural, and electronic properties of these materials. The book also reviews the theoretical work done in the field and concludes with technological applications.

Michel Houssa Laboratoire Materiaux et Microelectronique de Provence, Universite de Provence, France Silicon Processing and Device Technology Division, IMEC, Belgium

Introduction
The need for high-k gate dielectrics and materials requirement
Deposition techniques
ALCVD, MOCVD, PLD, MBE
Characterization
Physico-chemical characterization
X-ray and electron spectroscopies
Oxygen diffusion and thermal stability
Defect characterization by ESR
Band alignment determined by photo-injection
Electrical characteristics
Theory of defects in high-k materials
Bonding constraints and defect formation at Si/high-k interfaces
Band alignment calculations
Electron mobility at the Si/high-k interface
Model for defect generation during electrical stress
Technological aspects
Device integration issues
Device concepts for sub-100 nm CMOS technologies
Transistor characteristics
Nonvolatile memories based on high-k ferroelectric layers

Erscheinungsdatum	15.01.2021
Verlagsort	London
Sprache	englisch
Maße	156 x 234 mm
Gewicht	453 g
Themenwelt	Naturwissenschaften ► Physik / Astronomie ► Elektrodynamik
Themenwelt	Technik ► Elektrotechnik / Energietechnik
ISBN-10	0-367-45444-0 / 0367454440
ISBN-13	978-0-367-45444-9 / 9780367454449
Zustand	Neuware