Robust Sigma Delta Converters (eBook)

And Their Application in Low-Power Highly-Digitized Flexible Receivers

Robert H.M. van Veldhoven, Arthur H.M. van Roermund (Autoren)

eBook Download: PDF

2011 | 2011
XXIV, 296 Seiten
Springer Netherland (Verlag)
978-94-007-0644-6 (ISBN)

Infos

Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC. The book proposes to categorize these requirements in 5 quality indicators which can be used to qualify a system, namely accuracy, robustness, flexibility, efficiency and emission. In the book these quality indicators are used to categorize Sigma Delta converter theory. A few highlights on each of these quality indicators are;

• Quality indicators: provide a means to quantify system quality.
• Accuracy: introduction of new Sigma Delta Modulator architectures.
• Robustness: a significant extension on clock jitter theory based on phase and error amplitude error models. Extension of the theory describing aliasing in Sigma Delta converters for different types of DACs in the feedback loop.
• Flexibility: introduction of a Sigma Delta converter bandwidth scaling theory leading to very flexible Sigma Delta converters.
• Efficiency: introduction of new Figure-of-Merits which better reflect performance-power trade-offs.
• Emission: analysis of Sigma Delta modulators on emission is not part of the book

The quality indicators also reveal that, to exploit nowadays advanced IC technologies, things should be done as much as possible digital up to a limit where system optimization allows reducing system margins. At the end of the book Sigma Delta converter implementations are shown which are digitized on application-, architecture-, circuit- and layout-level.

Robust Sigma Delta Converters is written under the assumption that the reader has some background in receivers and in A/D conversion.

Robert H.M. van Veldhoven was born in Eindhoven, The Netherlands, in 1972. After finishing his pre-education (HAVO) at ''Het Hertog-Jan College'' in Valkenswaard, he started to study ''hands-on'' electronics at the MTS ''Leonardo Da Vinci college'' in Eindhoven. After 2 years at the MTS, he started studying electrical engineering at the polytechnical college ''Fontys Hogescholen'' in Eindhoven. In 1996 he joined the Mixed-Signal Circuits and Systems group at Philips Research after successfully finishing his graduation project on a low-power Sigma Delta modulator for multi-meter applications. After working 3 years at Philips he started to pursue a master degree in Electronics from the Technical University of Eindhoven, which he successfully finished in 2003. After working for 10 years at Philips Research, he joined the Mixed-Signal Circuits and Systems group at NXP Semiconductor Research in Eindhoven in 2006, where he is an expert in the field of high-resolution A/D and D/A converters, and integrated circuits for instrumentation-, sensor-, audio-, and radio-systems. In 2010 he pursued a PhD degree in Electronic Engineering. Van Veldhoven holds various US patents and published various papers at leading conferences and in leading journals, and is reviewer for several professional journals and conferences. In 2004 and 2010, he was invited to give a forum presentation at the ISSCC about sd modulators for wireless and cellular receivers.

Arthur H.M. van Roermund (SM'95) was born in Delft, The Netherlands in 1951. He received the M.Sc. degree in electrical engineering in 1975 from the Delft University of Technology and the Ph.D. degree in Applied Sciences from the K.U.Leuven, Belgium, in 1987. From 1975 to 1992 he was with Philips Re­search Laborato­ries in Eindhoven. From 1992 to 1999 he has been a full pro­fessor at the Electrical Engineer­ing Department of Delft Universi­ty of Technol­ogy, where he was chairman of the Elec­tronics Research Group and member of the management team of DIMES. From 1992 to 1999 he has been chairman of a two-years post-graduate school for 'chartered designer'. From 1992 to 1997 he has been consultant for Philips. October 1999 he joined Eindhoven University of Technology as a full professor, chairing the Mixed-signal Microelectronics Group. Since September 2002 he is also director of research of the Department of Electrical Engineering. He is chairman of the board of ProRISC, a nation-wide microelectronics platform; a member of the ICT research platform for the Netherlands (IPN); and a member of the supervisory board of the NRC Photonics research centre. Since 2001, he is one of the three organisers of the yearly workshop on Advanced Analog Circuit Design (AACD). In 2004 he achieved the 'Simon Stevin Meester' award, coupled to a price of 500.000€, for his scientific and technological achievements. In 2007 he was member of an international assessment panel for the Department of Electronics and Information of Politecnico di Milano, and in 2009 for Electronics and Electrical Engineering for the merged Aalto University Finland. He authored/co-authored more than 300 articles and 25 books.

 

Inhalt

Preface 6
Contents 7
List of Abbreviations 12
Terminology 16
List of Symbols 18
Nomenclature 21
Introduction 22
Advanced, Multi-standard Cellular and Connectivity Terminals for the Mass Market 23
Complexity: Mobile Phone Trends, Its Impact on the Transceiver and the Quest for Integration 24
Implications of Trends on the ADC Specification Generalized in Quality Indicators 27
Transistor Scaling: VLSI and Moore 28
Transistor Scaling in the Context of Shannon's Channel-Capacity Theorem 30
Smarter Circuits: Sigma Delta Modulators for Mobile Applications 30
Book Aims 31
Book Scope 32
Outline 32
System Quality Indicators 34
The System Function and Its In- and Outputs 35
System Quality 36
Accuracy 37
Robustness to Secondary Inputs 37
Flexibility 37
Efficiency 38
Emission of Secondary Outputs 38
The Digital Revolution 39
The Analog-Digital Interface 40
Digital Systems and the Quality Indicators 41
Accuracy 41
Robustness 42
Flexibility 43
Efficiency 43
Emission 44
Conclusions 44
Integrated Receiver Architectures for Cellular and Connectivity 48
Wireless Receiver Architectures for Digital Communication 48
Receiver Architecture and the Quality Indicators 51
Conclusions 52
Specifications for A/D Converters in Cellular and Connectivity Receivers 53
IF Choice 54
Image Rejection 54
Zero IF Architecture 55
Near Zero and High IF Architecture 57
IF Assessment 58
DC Offset and 1/f Noise 58
RF Front-End and ADC 1/f-Thermal Noise Corner Frequency 61
Top-End of the ADC DR 65
Signal Levels, Selectivity, and Maximum ADC Input Signal 66
Crest Factor 68
Receiver Gain 69
Narrow vs. Broad Band AGC 70
Bottom-End of the ADC DR 70
Receiver SNR Requirement 70
Receiver Noise Figure and ADC Noise Floor 71
DR of the ADC 73
DR of a Quadrature ADC 73
RF Front-End and ADC Linearity Requirements 74
Second and Third Order Harmonic Distortion 74
Second and Third Order Intermodulation and IP2 and IP3 75
Third Order Cross-Modulation 78
Distortion in a Quadrature ADC 79
Example Receiver Partitioning: Receiver for a GSM Mobile Phone 81
IF Choice and Image Rejection 82
Top-End of the ADC Dynamic Range 83
Receiver Sensitivity Requirement and the Bottom-End of the ADC Dynamic Range 85
Receiver Linearity Requirement and ADC Linearity 86
ADC Requirements, the System Quality Indicators and Sigma Delta Modulators as the ADC Architecture 87
Conclusions 90
Sigma Delta Modulator Algorithmic Accuracy 91
Sigma Delta Modulators with 1-bit Quantizer and 1-bit DAC 93
Sigma Delta Modulators with b-bit Quantizer and b-bit DAC 98
Sigma Delta Modulators with 1.5-bit Quantizer and DAC 99
Sigma Delta Modulators with Multiple Quantizers and 1-bit DAC 100
Sigma Delta Modulators with Additive Error-Feedback Loops 102
Cascaded Sigma Delta Modulators 107
Conclusions 108
Sigma Delta Modulator Robustness 110
Portable, Technology Robust Analog IP and Time-to-Market 111
Technology Scaling and Its Impact on Analog Design Parameters 112
A Design Methodology to Increase the Portability of Analog IP 113
Continuous Time vs. Discrete Time Loop Filter 116
Feed-Forward vs. Feedback Loop Filter 118
Gain Accuracy 120
Sigma Delta Modulator with 1-bit Quantizer and 1-bit DAC 120
Sigma Delta Modulator with b-bit Quantizer and b-bit DAC 120
Sigma Delta Modulator with Multiple Quantizers and 1-bit DAC 120
Sigma Delta Modulator with Additive Error Feedback Loops 121
Cascaded Sigma Delta Modulators 123
Circuit Noise of the Modulator's Input Stage and DAC 124
RC Integrator Input Stage and SI Feedback DAC 124
RC Integrator Input Stage and SR Feedback DAC 125
RC Integrator Input Stage and SC Feedback DAC 125
Impact of Supply Voltage on the Circuit Noise Requirements 126
Non-linearity 127
Non-linearity in the Input Stage 127
Non-linearity of Differential Pairs 128
Non-linearity of a Sigma Delta Modulator Input Stage 129
Non-linearity in the Quantizer Decision Levels 130
Inter-Symbol-Interference in the Feedback DAC 131
Non-linearity in the Output Levels of the Feedback DAC 132
Non-linearity in the Output Levels of a 1-bit DAC 132
Non-linearity in the Output Levels of a b-bit DAC 132
Non-linearity in the Output Levels of a 1.5-bit DAC 133
Aliasing in Sigma Delta Modulators 135
Aliasing in the Quantizer 135
Sigma Delta Modulator with an SI Feedback DAC 136
Simulations 138
Sigma Delta Modulator with an SR Feedback DAC 139
Mismatch Between Data Switches and RTZ Switch 139
Inter Data Switch Mismatch 140
Simulations 141
Sigma Delta Modulator with an SC Feedback DAC 141
Excess Loop Delay 146
Excess Time Delay Compensation 147
Excess Phase Compensation 148
DAC Feedback Pulse Shape and Delay 150
Clock Jitter in CT Sigma Delta Modulators 151
The TAJE Model 152
CT 1-bit Sigma Delta Modulator with SI DAC 153
CT 1-bit Sigma Delta Modulator with RTZ SI DAC 153
CT 1-bit Sigma Delta Modulator with RTZ SC DAC 155
The TAJE Model: SI Versus SC Feedback DAC 156
TAJE Model Summary 157
The TPJE Model: Sine Wave Induced Jitter 158
Sigma Delta Modulator with SC DAC 159
Amplitude Modulation 160
Phase Modulation 160
Combination of Amplitude and Phase Modulation 161
Sigma Delta Modulator with SI DAC 162
Amplitude Modulation 162
Phase Modulation 163
Combination of Amplitude and Phase Modulation 164
Application of the Sine Wave Induced Jitter Model 164
Verification of the TPJE Model with Sine Wave Induced Clock Jitter 165
The TPJE Model: Substitution of White Noise Jitter in the Sine Wave Induced Jitter Model 170
Sigma Delta Modulator with SC DAC 170
Sigma Delta Modulator with SI DAC 173
Verification of the TPJE Model with White Noise Induced Clock Jitter 175
The TPJE Model: SI Versus SC Feedback DAC 180
The TPJE Model: An Application Driven Choice Between SI Versus SC Feedback DAC 181
Modulators with a Top-End DR Determined by In-band Signals 181
Modulators with a Top-End DR Determined by Out-of-Band Signals 183
Conclusions 188
Sigma Delta Modulator Flexibility 194
Receiver Dictated Flexibility Requirements 194
Sigma Delta Modulator Clock Flexibility 196
Receiver Architecture with LO-Dependent ADC Clock 197
Receiver Architecture with a Flexible and Independent Clock for the ADC 198
Receiver Architecture with Fixed, Independent ADC Clock 199
Choice of Clock Strategy 201
Input Stage and DAC Flexibility 202
Loop-Filter Flexibility 202
Quantizer Flexibility 204
Conclusions 205
Sigma Delta Modulator Efficiency 207
Power Efficiency FOM: FOMDR 209
Benchmarking with FOMDR 211
Power Efficiency FOM: FOMeq,th 212
Benchmarking with FOMeq,th 215
Distortion FOM: FOMHD3D 218
Benchmarking with FOMHD3D 220
Area FOM: FOMarea 223
Benchmarking with FOMarea 227
Conclusions 229
Sigma Delta Modulator Implementations and the Quality Indicators 230
Digitization at System/Application Level: Sigma Delta Modulators for Highly Digitized Receivers 231
A 1.5-bit Sigma Delta Modulator for UMTS 232
System Architecture 232
Modulator Architecture 232
Circuit Design 234
Experimental Results 236
Conclusions 238
A Triple-Mode Sigma Delta Modulator for GSM-EDGE, CDMA2000 and UMTS 239
System Architecture 240
Sigma Delta Modulator Architecture 240
Circuit Design 242
Experimental Results 245
Conclusions 248
An Extremely Scalable Sigma Delta Modulator for Cellular and Wireless Applications 249
System Architecture 249
Sigma Delta Modulator Architecture 249
Experimental Results 252
Conclusions 255
Multi-mode Modulator Clock Strategy 255
Digitization at Analog IP Architecture Level: A Hybrid, Inverter-Based Sigma Delta Modulator 257
Sigma Delta Modulator Architecture 258
Circuit Design 259
Experimental Results 262
Conclusions 265
Digitization at Circuit and Layout Level: Technology Portable Sigma Delta Modulators 266
Sigma Delta Modulator Architecure 267
Circuit Design and Layout 268
Experimental Results 271
Conclusions 273
Implementations Judged on the FOMs and Quality Indicators 274
Conclusions 277
Conclusions 279
Harmonic and Intermodulation Distortion in an I& Q System
Double Sided Spectrum of Second and Third Order Distortion of a Complex Signal 281
Double Sided Spectrum of Second and Third Order Distortion in a Complex System 282
Distortion of a Differential Input Transistor Pair Biased in Weak Inversion 284
Fourier Series Expansion and Return-to-Zero 285
Clock Jitter in an I& Q System According to the TPJE Clock Jitter Model
References 288
Index 301

Produkt-Details

• Erscheint lt. Verlag: 30.1.2011
• Reihe/Serie: Analog Circuits and Signal Processing
• Reihe/Serie: Analog Circuits and Signal Processing
• Zusatzinfo: XXIV, 296 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Naturwissenschaften ► Physik / Astronomie
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Aliasing • Analog Circuit Design • Clock Jitter • Delay compensation • Receiver specification (quality indicators) • Sigma Delta Converter
• ISBN-10: 94-007-0644-8 / 9400706448
• ISBN-13: 978-94-007-0644-6 / 9789400706446