ESD Protection Device and Circuit Design for Advanced CMOS Technologies (eBook)

Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev (Autoren)

eBook Download: PDF

2008 | 2008
XVIII, 228 Seiten
Springer Netherland (Verlag)
978-1-4020-8301-3 (ISBN)

Infos

ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.

Manoj Sachdev has (co)authored several books for Springer/Kluwer

Inhalt

Dedication. Preface. Acknowledgments. 1. INTRODUCTION. 1. Nature of ESD phenOmena. 2. ESD failures in nanometric technologies. 3. Circuit reliability: ESD models. 4. ESD challenges for advanced CMOS technologies. 5. ESD design window. 6. Book objective and organization. 7. Summary. 2. ESD MODELS AND TEST METHODS. 1. Introduction. 2. ESD zapping modes. 3. HBM model. 4. MM model. 5. CDM model. 6. CBM model. 7. TLP testing. 8. Correlation of ESD test methods. 9. ESD testers. 10. Summary. 3. ESD DEVICES FOR INPUT/OUTPUT PROTECTION. 1. Introduction. 2. Non-snapback devices. 3. Snapback devices. 4. Latch-up in ESD protection devices. 5. ESD devices under stress conditions: Burn in. 6. Failure criteria of ESD devices. 7. Summary. 4. CIRCUIT DESIGN CONCEPTS FOR ESD PROTECTION. 1. Introduction. 2. ESD protection networks. 3. Distributed ESD protection networks. 4. Circuit design flow for ESD. 5. Summary. 5. ESD POWER CLAMPS. 1. Introduction. 2. Static ESD clamp. 3. Transient power clamps. 4. Summary. 6. ESD PROTECTION CIRCUITS FOR HIGH-SPEED I/OS. 1. Introduction. 2. Parasitic capacitance of ESD protection circuits. 3. A 12-bit 20Ms/s analog to digital converter [3]. 4. A 14-bit 125Ms/s analog to digital converter [5]. 5. A 4Gb/s current mode logic driver [9]. 6. Summary. 7. ESD PROTECTION FOR SMART POWER APPLICATIONS. 1. Introduction. 2. LDMOS-based ESD protection. 3. BJT-based ESD protection. 4. SCR-based ESD protection. 5. Power bus ESD protection circuits for high voltage applications. 6. summary. 8. ESD PROTECTION FOR RF CIRCUITS. 1. Introduction. 2. Basic concepts. 3. Low noise amplifer. 4. ESD protection methods for RF circuits. 5. Summary. 9. CONCLUSION. 1. Introduction. 2. Future work. Index.

Produkt-Details

• Erscheint lt. Verlag: 26.4.2008
• Zusatzinfo: XVIII, 228 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Naturwissenschaften ► Physik / Astronomie
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Maschinenbau
• Themenwelt: Technik ► Nachrichtentechnik
• Schlagworte: bipolar junction transistor • bipolar power transistor • Circuit and device reliability • Circuit and device simulation • CMOS • Double-diffused metal-oxide-semiconductor transistor • Electrical overstress (EOS) • Electrostatic discharge (ESD) • Integrated circuit • Latch-up • Logic • VLSI
• ISBN-10: 1-4020-8301-7 / 1402083017
• ISBN-13: 978-1-4020-8301-3 / 9781402083013