High Performance Embedded Architectures and Compilers
Springer Berlin (Verlag)
978-3-540-77559-1 (ISBN)
Prof. Dr. Theo Ungerer ist Professor für Systemnahe Informatik mit Schwerpunkt Kommunikationssysteme und Internet-Anwendungen am Institut für Informatik der Universität Augsburg. Zudem ist er wissenschaftlicher Direktor des Rechenzentrums und Mitglied des Lenkungsrates des IT-Servicezentrums der Universität Augsburg. Seine wissenschaftlichen Interessen gelten den Gebieten der Prozessorarchitektur sowie der eingebetteten und ubiquitären Systeme. Theo Ungerer hat über 150 wissenschaftliche Publikationen und 6 Fachbücher veröffentlicht. Er ist Mitglied des Lenkungsrates und deutscher Koordinator des EU-Exzellenznetzwerkes HiPEAC- High Performance Embedded Architectures and Compilers
Invited Program.- Supercomputing for the Future, Supercomputing from the Past (Keynote).- I Multithreaded and Multicore Processors.- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing.- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect.- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE.- IIa Reconfigurable - ASIP.- BRAM-LUT Tradeoff on a Polymorphic DES Design.- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.- IIb Compiler Optimizations.- Fast Bounds Checking Using Debug Register.- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.- III Industrial Processors and Application Parallelization.- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.- Experiences with Parallelizing a Bio-informatics Program on the Cell BE.- Drug Design Issues on the Cell BE.- IV Power-Aware Techniques.- Coffee: COmpiler Framework for Energy-Aware Exploration.- Integrated CPU Cache Power Management in Multiple Clock Domain Processors.- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.- V High-Performance Processors.- The Significance of Affectors and Affectees Correlations for Branch Prediction.- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator.- LPA: A First Approach to the Loop Processor Architecture.- VI Profiles: Collection and Analysis.- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm.- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy.- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior.- VII Optimizing Memory Performance.- MLP-Aware Dynamic Cache Partitioning.- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory.- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
| Erscheint lt. Verlag | 15.1.2008 |
|---|---|
| Reihe/Serie | Lecture Notes in Computer Science | Theoretical Computer Science and General Issues |
| Zusatzinfo | XIII, 400 p. |
| Verlagsort | Berlin |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Gewicht | 635 g |
| Themenwelt | Informatik ► Theorie / Studium ► Algorithmen |
| Informatik ► Weitere Themen ► Hardware | |
| Schlagworte | algorithms • Compiler • compiler techniques • Complexity • Computer Architecture • dataflow programming • dynamic compilation • Embedded Systems • extensible processors • Hardcover, Softcover / Informatik, EDV/Informatik • HC/Informatik, EDV/Informatik • high-performance architecture • memory system optimization • Network Computing • network processors • Parallel Architectures • Performance Evaluation • Processor • Processor Architectures • Program Optimization • Random Access Memory • reconfigurable architectures • secured computing • security processors • system-on-chip architecture • Systems Architecture • Variable |
| ISBN-10 | 3-540-77559-5 / 3540775595 |
| ISBN-13 | 978-3-540-77559-1 / 9783540775591 |
| Zustand | Neuware |
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