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SystemVerilog for Verification

A Guide to Learning the Testbench Language Features

(Autor)

Buch | Hardcover
468 Seiten
2008 | 2nd Revised edition
Springer-Verlag New York Inc.
978-0-387-76529-7 (ISBN)

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SystemVerilog for Verification - Chris Spear
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This expanded book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. It contains a new chapter covering programs and interfaces as well as chapters with updated information.
The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C.

Zusatzinfo 1, black & white illustrations
Verlagsort New York, NY
Sprache englisch
Maße 156 x 234 mm
Gewicht 1830 g
Einbandart gebunden
Themenwelt Mathematik / Informatik Informatik Grafik / Design
Mathematik / Informatik Informatik Theorie / Studium
Technik Elektrotechnik / Energietechnik
ISBN-10 0-387-76529-8 / 0387765298
ISBN-13 978-0-387-76529-7 / 9780387765297
Zustand Neuware
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