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Fast, Efficient and Predictable Memory Accesses

Optimization Algorithms for Memory Architecture Aware Compilation
Buch | Hardcover
258 Seiten
2006
Springer-Verlag New York Inc.
978-1-4020-4821-0 (ISBN)

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Fast, Efficient and Predictable Memory Accesses - Lars Wehmeyer, Peter Marwedel
CHF 149,75 inkl. MwSt
Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

Prof. Peter Marwedel is well established within the Electronic Design Automation community, he has co-authored four books with us and also published his best-selling Embedded Systems Design (text)book with Springer.

Abstract.- Models and Tools.- Scratchpad Memory Optimizations.- Main Memory Optimizations.- Register File Optimization.- Summary.- Future Work.

Erscheint lt. Verlag 12.7.2006
Zusatzinfo XII, 258 p.
Verlagsort New York, NY
Sprache englisch
Maße 155 x 235 mm
Themenwelt Mathematik / Informatik Informatik Betriebssysteme / Server
Mathematik / Informatik Informatik Theorie / Studium
Technik Elektrotechnik / Energietechnik
ISBN-10 1-4020-4821-1 / 1402048211
ISBN-13 978-1-4020-4821-0 / 9781402048210
Zustand Neuware
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