Logic-timing Simulation And The Degradation Delay Model

Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia (Autoren)

Buch | Hardcover

288 Seiten

2005
Imperial College Press (Verlag)
978-1-86094-589-2 (ISBN)

Titel z.Zt. nicht lieferbar
Versandkostenfrei
Auch auf Rechnung

Artikel merken

Provides the reader with a background in the field of logic-timing simulation and delay modeling. This book includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. It also explores the capabilities of logic-timing using research results.

This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s)

# Fundamentals of Timing Simulation # Delay Models: Evolution and Trends # Degradation and Inertial Effects # CMOS Inverter Degradation Delay Model # Gate-Level DDM # Logic Level Simulator Design and Implementation # DDM Simulation Results # Accurate Measurement of the Switching Activity

Verlagsort	London
Sprache	englisch
Themenwelt	Informatik ► Grafik / Design ► Digitale Bildverarbeitung
ISBN-10	1-86094-589-9 / 1860945899
ISBN-13	978-1-86094-589-2 / 9781860945892
Zustand	Neuware