Logic Synthesis and SOC Prototyping

RTL Design using VHDL

Vaibbhav Taraate (Autor)

Buch | Hardcover

251 Seiten

2020 | 1st ed. 2020
Springer Verlag, Singapore
978-981-15-1313-8 (ISBN)

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This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Introduction.- ASIC Design and SOC prototype.- Design using VHDL & Guidelines.- Design using VHDL & Guidelines.- Design and Verification Strategies.- VHDL Design and RTL Tweaks.- ASIC Synthesis and Design Constraints.- Design optimization.- Design optimization.- FPGA for SOC Prototype.- Prototype using Single and Multiple FPGA.

Erscheinungsdatum	06.03.2020
Zusatzinfo	XIX, 251 p.
Verlagsort	Singapore
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Informatik ► Theorie / Studium ► Algorithmen
	Informatik ► Weitere Themen ► Hardware
	Technik ► Elektrotechnik / Energietechnik
ISBN-10	981-15-1313-9 / 9811513139
ISBN-13	978-981-15-1313-8 / 9789811513138
Zustand	Neuware