A Practical Approach to VLSI System on Chip (SoC) Design (eBook)

A Comprehensive Guide

Veena S. Chakravarthi (Autor)

eBook Download: PDF

2019 | 1st ed. 2020
XXXII, 312 Seiten
Springer International Publishing (Verlag)
978-3-030-23049-4 (ISBN)

Infos

This book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs.

• A comprehensive practical guide for VLSI designers;
• Covers end-to-end VLSI SoC design flow;
• Includes source code, case studies, and application examples.

Dr. Veena S. Chakravarthi has more than two decades of semiconductor industry experience in managing design and development of large multiprocessor SoCs, with around six multimillion gate tape outs to her credit. She obtained her PhD in Electronics Engineering from Bangalore University in 2008. Dr. Chakravarthi is co-founder and Chief Technology Officer of Sensesemi Technologies, a healthcare startup based in Bangalore. Prior to that, she has worked for ITI Limited, Mindtree Consulting Pvt. Ltd., Centillium India Pvt. Ltd., and Transwitch India Pvt. Ltd., and consulted for Ikanos Communications, Pereira Ventures, and Asarva Chips and Technologies in various capacities. She has published many papers and filed two patents in the area of VLSI and healthcare. She has been associated with the research center in the Electronics & Communication Engineering Department at BNM Institute of Technologies, Bangalore. Her areas of research interest include low-power high performance SOC designs in EPON, communication, and wireless technologies. She is currently Vice Chair of the Bangalore Section Chapter of the IEEE Nanotechnology Council, and organized many events including the recent IISc IEEE Nanotechnology Summer School in July 2018.

Inhalt

Foreword 7
Foreword 9
Foreword 11
Preface 13
Why This Book? 16
Why One Should Read This Book? 16
What Problem Does It Solve? 16
Who Are the Audience? 17
What Are the Prerequisites to Read This Book? 17
Why Become VLSI Designer? 17
How Is the Book Organized? 18
References 18
Contents 19
Abbreviations and Acronyms 25
Chapter 1: Introduction 29
1.1 Introduction to VLSI 29
1.2 Application Areas of SOC 29
1.3 Trends in VLSI 30
1.3.1 Complexity 30
1.3.2 VLSI Circuit to System on Chip 31
1.3.3 Speed of Operation 32
1.3.4 Die Size 34
1.3.5 Design Methodology 34
1.4 SOC Design and Development 36
1.5 Skill Set Required 36
1.6 EDA Environment 37
1.7 Challenges in All 37
References 38
Chapter 2: System on Chip (SOC) Design 39
2.1 System on Chip (SOC) 39
2.2 Constituents of SOC 39
2.2.1 Processor Cores 42
2.2.2 Embedded Memory Core 44
2.2.3 Analog Cores 44
2.2.4 Interface Cores 44
2.3 SOC Development Life Cycle 46
2.3.1 SOC Design Requirements 48
2.3.2 Design Strategy 49
2.3.3 SOC Design Planning 49
2.3.4 System Modelling 50
2.3.5 System Module Development Feasibility Study 50
2.3.6 IP Design Decisions 51
2.3.7 Verification IPs 51
2.3.8 Target Technology Decision 51
2.3.9 Development Plan 52
2.3.10 EDA Tool Plan 53
2.4 Design Center Infrastructure 53
2.4.1 Computational Servers 54
2.4.2 Filers 54
2.4.3 Workstations 55
2.4.4 Backup Servers 55
2.4.5 Source Control Server 55
2.4.6 Firewalls 56
2.4.7 Resource Planning 56
2.5 SOC Design Flow 56
2.5.1 SOC Chip High-Level Design Methodology 57
2.5.2 Digital SOC Core Development Flow 57
2.5.3 Processor Subsystem Core Design 60
2.5.4 SOC Integrated Design Flow 62
2.5.5 Low-Power SOC Design 62
2.5.6 EVM Design Development Flow 63
2.5.7 Software Development Flow 64
2.5.8 Product Integration Flow 68
Chapter 3: SOC Constituents 69
3.1 Embedded Processor Subsystem for System on Chip 69
3.1.1 Choice of Embedded Processor for SOC 70
3.1.2 Embedded General-Purpose RISC Processors 70
3.1.3 DSP Processors 74
3.1.4 Issues of hw-sw Co-design 75
3.1.5 Processor Subsystems 75
3.1.6 Processor Configuration Tools 76
3.1.7 Development Boards 77
3.2 Embedded Memories 78
3.2.1 Types of Memories 79
3.2.2 Choice of Memories 79
3.2.3 Memory Compiler and Compiled Memories 79
3.3 Protocol Blocks 81
3.4 Mixed Signal Blocks 82
3.5 RF Control Blocks 84
3.6 Analog Blocks 84
3.7 Third-Party IP Cores 85
3.8 System Software 85
3.8.1 OSI System Model 85
Physical Layer (Layer 1) 86
Data Link Layer (Layer 2) 86
Network Layer (Layer 3) 87
Transport Layer (Layer 4) 87
Session Layer (Layer 5) 87
Presentation Layer (Layer 6) 87
Application Layer (Layer 7) 87
3.9 GAMP Classification of Software 87
3.9.1 Hardware 88
3.9.2 Device Driver 88
3.9.3 Firmware 88
3.9.4 Middleware 89
3.9.5 Software 89
3.9.6 Cloud 89
3.10 Design-Specific Blocks 89
References 89
Chapter 4: VLSI Logic Design and HDL 90
4.1 VLSI Logic Design Concepts 90
4.1.1 Synchronous Sequential Circuits 90
4.2 Metastability 92
4.3 Asynchronous Circuits 92
4.4 Asynchronous and Synchronous Resets 94
4.5 Clock Domain Crossovers 94
4.6 Speed Matching 94
4.7 Combinational and Synchronous Logic 96
4.8 Finite State Machines (FSMs) 96
4.9 Standard Cells and Compiled Logic Blocks 97
4.10 Hard and Soft Macros 97
4.11 Concept of Buffers 98
4.12 Hardware Accelerator 98
4.13 Design Assertions 99
4.14 Low-Power Design Techniques 99
4.15 Hardware Description Languages (HDLs) 101
4.16 Behavioral Modelling of the Hardware System 103
4.17 Dataflow Modelling of the Hardware System 103
4.18 Structural Modelling of the Hardware System 103
4.19 Input-Output Pad Instantiation 105
4.19.1 Power Ground Corner Pad Instantiation 107
References 107
Chapter 5: SOC Synthesis 108
5.1 SOC Synthesis 108
5.1.1 Set Synthesis Environment 111
5.1.2 Read Library 111
5.1.3 HDL Files 111
5.1.4 Elaborate Design Files 112
5.1.5 Read Constraints 112
5.1.6 Optimization Constraint 112
5.1.7 Synthesis 113
5.1.8 Analyze 113
5.1.9 Write Reports 114
5.1.10 Design Constraints 114
5.2 Design Rule Constraints (DRC) 115
5.3 SOC Design Synthesis 116
5.4 High Fanout Nets (HFNs) 117
5.5 Low-Power Synthesis 118
5.5.1 Introduction to Low-Power SOCs 118
5.5.2 Universal Power Format (UPF) 121
5.6 Reports 121
5.6.1 Generating an Area Report 123
5.6.2 Gate Level Netlist Verification 123
References 124
Chapter 6: Static Timing Analysis (STA) 125
6.1 SOC Timing Analysis 125
6.2 Timing Definition 125
6.3 Timing Delay Calculation Concepts 130
6.4 Timing Analysis 130
6.5 Modelling Process, Voltage, and Temperature Variations 135
6.5.1 Equivalent Cells 135
6.6 Timing and Design Constraints 136
6.7 Organizing Paths to Groups 138
6.8 Design Corners 140
6.9 Challenges of STA During SOC design 141
Reference 142
Chapter 7: SOC Design for Testability (DFT) 143
7.1 Need for Testability 143
7.2 SOC Design for Testability Guidelines 143
7.3 DFT Logic Insertion Techniques 146
7.3.1 Scan Insertion 146
7.4 Boundary Scan 148
7.5 Boundary Scan Insertion Flow 151
7.6 Memory Built- In Self-Test (MBIST) 151
7.6.1 Stuck-at Faults 154
7.6.2 Transition Faults 154
7.6.3 Coupling Faults 155
7.6.4 Neighborhood Pattern-Sensitive Faults 156
7.6.5 MBIST Algorithms 157
7.7 ROM Test Algorithm 157
7.8 Power Aware Test Module Insertion (PATM) 158
7.8.1 Logic BIST Insertion 158
7.8.2 Writing Out DFT SDC 161
7.8.3 Compression Insertion 162
7.9 On-SOC Clock Generation (OSCG) Insertion 162
7.10 Challenges in SOC DFT 163
7.11 Memory Clustering 163
7.12 DFT Simulations 164
7.13 ATPG Pattern Generation 164
7.14 Automatic Test Equipment Testing (ATE Testing) 164
7.15 DFT Tools 165
Chapter 8: SOC Design Verification 166
8.1 Importance of Verification 166
8.2 Verification Plan and Strategies 168
8.3 Verification Plan 169
8.4 Functional Verification 171
8.5 Verification Methods 172
8.6 Design for Verification 172
8.7 Verification Example 176
8.8 Verification Tools 185
8.9 Verification Language 190
8.10 Automation Scripts 190
8.11 Verification Reuse and Verification IPs 191
8.12 Universal Verification Methodology (UVM) 192
8.12.1 Low-Power Design Verification 193
8.12.2 Low-Power Gate-Level Simulation 193
8.13 Bug and Debug 193
8.13.1 Bug Tracking Workflow 194
8.14 Formal Verification 194
8.15 FPGA Validation 196
8.16 Validation on Development Boards 197
References 197
Chapter 9: SOC Physical Design 198
9.1 Re-convergent Model of VLSI SOC Design 198
9.2 File Formats 199
9.3 SOC Physical Design 199
9.3.1 Physical Design Theory 202
9.3.2 Stick Diagrams 202
9.4 Physical Design Setup and Floor Plan 208
9.5 Floor Planning 209
9.6 Placement 210
9.7 Physical Design Constraints 211
9.8 Clock Tree Synthesis (CTS) 212
9.9 Routing 215
9.10 ECO Implementation 216
9.11 Advanced Physical Design of SOCs 217
9.11.1 For Low Power 217
9.11.2 For Advanced Technology 219
9.12 High Performance 219
9.13 Photolithography and Mask Pattern 220
References 224
Chapter 10: SOC Physical Design Verification 225
10.1 SOC Design Verification by Formal Verification 225
10.1.1 Model Checking 225
10.1.2 Equivalence Checking 227
10.2 STA Analysis 229
10.3 ECO Checks 231
10.4 Electromigration 231
10.5 Simultaneous Switching Noise (SSN) 231
10.6 Electrostatic Discharge (ESD) Protection 232
10.7 IR and Cross Talk Analysis 233
10.8 Gate-Level Simulation 234
10.9 Electrical Rule Check (ERC) 234
10.10 DRC Rule Check 235
10.11 Design Rule Violation (DRV) Checks 235
10.12 Design Tape-Out 237
References 238
Chapter 11: SOC Packaging 239
11.1 Introduction to VLSI SOC Packaging 239
11.2 Classification of Packages 240
11.3 Criteria for Selection of Packages 240
11.4 Package Components 241
11.5 Package Assembly Flow 242
11.6 Packaging Technology 243
11.7 Flip-Chip Packages 245
11.8 Typical Packages 246
11.9 Package Performance 246
11.10 System Integration 246
Chapter 12: Reference Designs 249
12.1 Design for Trial 249
12.2 Prerequisites 249
12.3 User Guidelines 249
12.4 Design Directory 250
12.5 Section 1 250
12.6 Design Examples 251
12.6.1 32-Bit Adder 251
12.6.2 Test Bench Module adder_tb 252
12.6.3 16 × 16 Multiplier 254
12.7 32-Bit Counter with Overflow 256
12.7.1 4:2 Encoder 270
12.8 Section 2 314
12.8.1 Design Flow 314
12.8.2 Executable Scripts 320
12.9 Section 3 324
12.9.1 Overview and Application Scenario 324
12.9.2 Mini-SOC Design 326
IO Diagram 326
Index 328

Produkt-Details

• Erscheint lt. Verlag: 25.9.2019
• Zusatzinfo: XXXII, 312 p. 204 illus.
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Clock Tree synthesis • Embedded Memory • Embedded Processor • Embedded Systems • Fabless design • Integrated Circuits • Memory compiler • semiconductor • SOC design • Standard cell library • Static Timing Analysis • System-on-Chip • UPF flow • Very Large Scale Integration • VLSI • VLSI-SoC
• ISBN-10: 3-030-23049-X / 303023049X
• ISBN-13: 978-3-030-23049-4 / 9783030230494