Designing Digital Computer Systems with Verilog
Cambridge University Press (Verlag)
978-0-521-82866-6 (ISBN)
This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.
DAVID LILJA received his PhD in Electrical Engineering from the University of Illinois at Urbana-Champaign. He is currently a Professor of Electrical and Computer Engineering , and a Fellow of the Minnesota Supercomputing Institute, at the University of Minnesota in Minneapolis. He also serves as a member of the graduate faculties in Computer Science and Scientific Computation, and was the founding Director of Graduate Studies for Computer Engineering. He has served on the program committees of numerous conferences and as associate editor for IEEE Transactions on Computers. David is a Senior member of the IEEE and a member of the ACM. SACHIN SAPATNEKAR received his PhD from the University of Illinois at Urbana-Champaign. Currently, he is the Robert and Marjorie Henle Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, and serves on the graduate faculty in Computer Science and Engineering. He has served as Associate Editor for several IEEE journals, a distinguished visitor for the IEEE Computer Society and a distinguished lecturer for the IEEE Circuits and Systems Society. He is a recipient of the NSF Career Award and the SRC Technical Excellence Award. He is a Fellow of the IEEE and a member of the ACM.
Preface; 1. Controlling complexity; 2. A verilogical place to start; 3. Defining the instruction set architecture; 4. Algorithmic behavioral modeling; 5. Building an assembler for VeSPA; 6. Pipelining; 7. Implementation of the pipelined processor; 8. Verification; Appendix A: the VeSPA instruction set architecture (ISA); Appendix B: the VASM assembler; Index.
| Erscheint lt. Verlag | 2.12.2004 |
|---|---|
| Zusatzinfo | 5 Tables, unspecified |
| Verlagsort | Cambridge |
| Sprache | englisch |
| Maße | 180 x 255 mm |
| Gewicht | 530 g |
| Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 0-521-82866-X / 052182866X |
| ISBN-13 | 978-0-521-82866-6 / 9780521828666 |
| Zustand | Neuware |
| Haben Sie eine Frage zum Produkt? |
aus dem Bereich
