Thread and Data Mapping for Multicore Systems
Springer International Publishing (Verlag)
978-3-319-91073-4 (ISBN)
It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures.
On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access.
Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.
Eduardo Henrique Molina da Cruz graduated, with honors, in Computer Science in the State University of Maringá (UEM) in 2009. He received his master's degree from the Postgraduate Program in Computing in the Informatics Institute of the Federal University of Rio Grande do Sul (UFRGS) in 2012. In 2016, he received his Ph.D., with honors, also by the Postgraduate Program in Computing at the Informatics Institute of the Federal University of Rio Grande do Sul (UFRGS). After the Ph.D., he worked as a postdoctoral researcher at the Federal University of Rio Grande do Sul (UFRGS). His research comprises the areas of computer architecture, operating systems and parallel and distributed processing. It focuses on optimizing the memory access in multicore and manycore architectures, as well as architectures with non-uniform access to memory (NUMA). Currently, he is a professor at Federal Institute of Parana (IFPR). Matthias Diener received his PhD degree in Computer Science from the Federal University of Rio Grande do Sul (UFRGS) and the TU Berlin in 2015. He is currently a postdoctoral researcher at the University of Illinois at Urbana-Champaign. His work focuses on adapting parallel applications to the hardware they are running on, through improving data locality, load balancing, and support for heterogeneous systems.
preface.- chapter 1: introduction.- chapter 2: Sharing-aware mapping and parallel architectures.- chapter 3: Sharing-aware mapping and parallel applications.- chapter 4: Sharing-Aware mapping methods.- chapter 5: Improving performance with Sharing-Aware mapping.- chapter 6: conclusion and research prospects.- index.
| Erscheinungsdatum | 15.07.2018 |
|---|---|
| Reihe/Serie | SpringerBriefs in Computer Science |
| Zusatzinfo | IX, 54 p. 34 illus. |
| Verlagsort | Cham |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Gewicht | 113 g |
| Themenwelt | Mathematik / Informatik ► Informatik ► Betriebssysteme / Server |
| Mathematik / Informatik ► Informatik ► Software Entwicklung | |
| Informatik ► Weitere Themen ► Hardware | |
| Schlagworte | Cache Memory • data mapping • Data movement • Non-uniform memory access • Thread Mapping |
| ISBN-10 | 3-319-91073-6 / 3319910736 |
| ISBN-13 | 978-3-319-91073-4 / 9783319910734 |
| Zustand | Neuware |
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