Intel Xeon Phi Processor High Performance Programming
Morgan Kaufmann Publishers In (Verlag)
978-0-12-809194-4 (ISBN)
- Titel ist leider vergriffen;
keine Neuauflage - Artikel merken
Intel® Xeon Phi™ Processor High-Performance Programming is useful even before you ever program a system with an Intel Xeon Phi processor. To help ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi processors, or other high-performance microprocessors. Applying these techniques will generally increase your program performance on any system and prepareyou better for Intel Xeon Phi processors.
Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years. James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012. Avinash Sodani is the chief architect of the Knights Landing Xeon Phi Processor. He has many years of experience architecting high end processors and previously was one of the architects for the first Core(tm) processor codenamed Nehalem.
Section I: Knights Landing1. Introduction2. Knights Landing overview3. Programming MCDRAM and Cluster modes4. Knights Landing architecture5. Intel Omni-Path Fabric6. µarch optimization advice
Section II: Parallel Programming7. Programming overview for Knights Landing8. Tasks and threads9. Vectorization10. Vectorization advisor11. Vectorization with SDLT12. Vectorization with AVX-512 intrinsics13. Performance libraries14. Profiling and timing15. MPI16. PGAS programming models17. Software-defined visualization18. Offload to Knights Landing19. Power analysis
Section III: Pearls20. Optimizing classical molecular dynamics in LAMMPS21. High performance seismic simulations22. Weather research and forecasting (WRF)23. N-Body simulation24. Machine learning25. Trinity workloads26. Quantum chromodynamics
| Erscheinungsdatum | 02.07.2016 |
|---|---|
| Verlagsort | San Francisco |
| Sprache | englisch |
| Maße | 191 x 235 mm |
| Gewicht | 1290 g |
| Themenwelt | Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge |
| Mathematik / Informatik ► Informatik ► Theorie / Studium | |
| Informatik ► Weitere Themen ► Hardware | |
| ISBN-10 | 0-12-809194-0 / 0128091940 |
| ISBN-13 | 978-0-12-809194-4 / 9780128091944 |
| Zustand | Neuware |
| Haben Sie eine Frage zum Produkt? |
aus dem Bereich
