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VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers

Andreas Burg, Ayse Coskun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis (Herausgeber)

Buch | Hardcover

X, 235 Seiten

2013 | 2013
Springer Berlin (Verlag)
978-3-642-45072-3 (ISBN)

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This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.

FPGA-Based High-Speed Authenticated Encryption System.- A Smart Memory Accelerated Computed Tomography Parallel Backprojection.- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure.- Spatially-Varying Image Warping: Evaluations and VLSI Implementations.- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.- Configurable Low-Latency Interconnect for Multi-core Clusters.- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture.- CMOS Implementation of Threshold Gates with Hysteresis.- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.

Erscheint lt. Verlag	22.11.2013
Reihe/Serie	IFIP Advances in Information and Communication Technology
Zusatzinfo	X, 235 p. 121 illus. in color.
Verlagsort	Berlin
Sprache	englisch
Maße	155 x 235 mm
Gewicht	537 g
Themenwelt	Mathematik / Informatik ► Informatik ► Netzwerke
	Mathematik / Informatik ► Informatik ► Theorie / Studium
	Informatik ► Weitere Themen ► Hardware
Schlagworte	adaptive routing • multi-core processor • Network-on-Chip • smart memory • threshold gates
ISBN-10	3-642-45072-5 / 3642450725
ISBN-13	978-3-642-45072-3 / 9783642450723
Zustand	Neuware