Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli (Autoren)

Buch | Softcover

112 Seiten

2012 | Softcover reprint of the original 1st ed. 2001
Springer-Verlag New York Inc.
978-1-4613-5573-1 (ISBN)

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This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.

1. Introduction.- 1.1 Cross-talk in DSM IC Design.- 1.2 Book Overview.- 1.3 Book Outline.- 2. Validating Deep Sub-Micron Effects.- 2.1 Chapter Overview.- 2.2 Trends in DSM VLSI Interconnect.- 2.3 Predicting VLSI Process Technology Trends.- 2.4 Extracting On-chip Layout Parasitics.- 2.5 Validating Cross-talk Effects.- 2.6 Review of Existing Techniques.- 2.7 Chapter Summary.- 3. VLSI Layout Fabrics.- 3.1 Chapter Overview.- 3.2 Our Dense Wiring Fabric (DWF).- 3.3 Advantages.- 3.4 Disadvantages.- 3.5 Chapter Summary.- 4. Fabric1 - Fabric Cell Based Design.- 4.1 Chapter Overview.- 4.2 Design Flow 1.- 4.3 Design Flow 2.- 4.4 Chapter Summary.- 5. Fabric3 - Network of PLA Based Design.- 5.1 Chapter Overview.- 5.2 Programmable Logic Arrays.- 5.3 Networks of Programmable Logic Arrays.- 5.4 Synthesis Algorithms for the Network of PLAs Methodology.- 5.5 Design Flow 1.- 5.6 Design Flow 2.- 5.7 Discussion.- 5.8 Chapter Summary.- 6. Wire Removal in a Network of PLAS.- 6.1 Chapter Overview.- 6.2 Binary SPFDs.- 6.3 MV-SPFDs.- 6.4 Experimental Results.- 6.5 Chapter Summary.- 7. Conclusions and Future Directions.- 7.1 Conclusions.- 7.2 Future Work.- Appendices.- Standard Cells.

Zusatzinfo	XIX, 112 p.
Verlagsort	New York, NY
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Informatik ► Weitere Themen ► CAD-Programme
Themenwelt	Technik ► Elektrotechnik / Energietechnik
ISBN-10	1-4613-5573-7 / 1461355737
ISBN-13	978-1-4613-5573-1 / 9781461355731
Zustand	Neuware