FPGAs: Instant Access (eBook)

Clive Maxfield (Autor)

eBook Download: PDF | EPUB

2011 | 1. Auflage
216 Seiten
Elsevier Science (Verlag)
978-0-08-056011-3 (ISBN)

Infos

FPGAs are central to electronic design! The engineers designing these devices are in need of essential information at a moment's notice. The Instant Access Series provides all the critical content that a computer design engineer needs in his or her daily work.

This book provides an introduction to FPGAs as well as succinct overviews of fundamental concepts and basic programming. FPGAs are a customizable chip flexible enough to be deployed in a wide range of products and applications. There are several basic design flows detailed including ones based in C/C++, DSP, and HDL. This book is filled with images, figures, tables, and easy to find tips and tricks for the engineer that needs material fast to complete projects to deadline.

Table of Contents

CHAPTER 1 The Fundamentals
CHAPTER 2 FPGA Architectures
CHAPTER 3 Programming (Configuring) an FPGA
CHAPTER 4 FPGA vs. ASIC Designs
CHAPTER 5 Traditional Design Flows
CHAPTER 6 Other Design Flows
CHAPTER 7 Using Design Tools
CHAPTER 8 Choosing the Right Device

*Tips and tricks feature that will help engineers get info fast and move on to the next issue
*Easily searchable content complete with tabs, chapter table of contents, bulleted lists, and boxed features
*Just the essentials, no need to page through material not needed for the current project

---

FPGAs are central to electronic design! The engineers designing these devices are in need of essential information at a moment's notice. The Instant Access Series provides all the critical content that a computer design engineer needs in his or her daily work. This book provides an introduction to FPGAs as well as succinct overviews of fundamental concepts and basic programming. FPGAs are a customizable chip flexible enough to be deployed in a wide range of products and applications. There are several basic design flows detailed including ones based in C/C++, DSP, and HDL. This book is filled with images, figures, tables, and easy to find tips and tricks for the engineer that needs material fast to complete projects to deadline. Tips and tricks feature that will help engineers get info fast and move on to the next issue Easily searchable content complete with tabs, chapter table of contents, bulleted lists, and boxed features Just the essentials, no need to page through material not needed for the current project

Inhalt

Front Cover 1
FPGAs: Instant Access 4
Copyright Page 5
Contents 6
About the Author 12
Chapter 1. The Fundamentals 14
Why Use FPGAs? 14
Applications 16
Some Technology Background 17
Fusible-link Technology 17
FPGA Programming Technologies 20
Instant Summary 25
Chapter 2. FPGA Architectures 26
More on Programming Technologies 27
SRAM-based Devices 27
Antifuse-based Devices 29
E[sup(2)]PROM/FLASH-based Devices 30
Hybrid FLASH-SRAM Devices 31
Fine-, Medium-, and Coarse-grained Architectures 31
Logic Blocks 32
MUX-based 32
LUT-based 33
LUT versus Distributed RAM versus SR 35
CLBs versus LABs versus Slices 36
Logic Cells/Logic Elements 37
Slicing and Dicing 37
CLBs and LABs 38
Distributed RAMs and Shift Registers 39
Embedded RAMs 40
Embedded Multipliers, Adders, etc. 40
Embedded Processor Cores 42
Hard Microprocessor Cores 43
Soft Microprocessor Cores 44
Clock Managers 45
Clock Trees 45
Clock Managers 46
General-purpose I/O 49
Configurable I/O Standards 49
Configurable I/O Impedances 50
Core versus I/O Supply Voltages 50
Gigabit Transceivers 51
Multiple Standards 52
Intellectual Property (IP) 53
Handcrafted IP 54
IP Core Generators 56
System Gates versus Real Gates 57
Instant Summary 60
Chapter 3. Programming (Configuring) an FPGA 62
Configuration Cells 63
Antifuse-based FPGAs 64
SRAM-based FPGAs 64
Programming Embedded (Block) RAMs, Distributed RAMs, etc. 65
Multiple Programming Chains 66
Quickly Reinitializing the Device 66
Using the Configuration Port 66
Serial Load with FPGA as Master 67
Parallel Load with FPGA as Master 68
Parallel Load with FPGA as Slave 69
Serial Load with FPGA as Slave 70
Using the JTAG Port 71
Using an Embedded Processor 72
Instant Summary 73
Chapter 4. FPGA vs. ASIC Designs 74
When You Switch from ASIC to FPGA Design, or Vice Versa 75
Coding Styles 75
Pipelining and Levels of Logic 75
Levels of Logic 77
Asynchronous Design Practices 78
Asynchronous Structures 78
Combinational Loops 78
Delay Chains 78
Clock Considerations 78
Clock Domains 78
Clock Balancing 78
Clock Gating versus Clock Enabling 79
PLLs and Clock Conditioning Circuitry 79
Reliable Data Transfer across Multiclock Domains 79
Register and Latch Considerations 80
Latches 80
Flip-flops with both "Set" and "Reset" Inputs 80
Global Resets and Initial Conditions 80
Resource Sharing (Time-Division Multiplexing) 80
Use It or Lose It! 80
But Wait, There's More 81
State Machine Encoding 81
Test Methodologies 82
Migrating ASIC Designs to FPGAs and Vice Versa 82
Alternative Design Scenarios 82
Instant Summary 86
Chapter 5. "Traditional" Design Flows 88
Schematic-based Design Flows 89
Back-end Tools like Layout 94
CAE + CAD = EDA 94
A Simple (early) Schematic-driven ASIC Flow 94
A Simple (early) Schematic-driven FPGA Flow 96
Flat versus Hierarchical Schematics 99
Schematic-driven FPGA Design Flows Today 101
HDL-based Design Flows 102
Advent of HDL-based Flows 102
A Plethora of HDLs 109
Points to Ponder 116
Instant Summary 119
Chapter 6. Other Design Flows 120
C/C++-based Design Flows 121
C versus C++ and Concurrent versus Sequential 123
SystemC-based Flows 125
Augmented C/C++-based Flows 130
Pure C/C++ -based Flows 133
Different Levels of Synthesis Abstraction 136
Mixed-language Design and Verification Environments 137
DSP-Based Design Flows 138
Alternative DSP Implementations 139
FPGA-centric Design Flows for DSPs 144
Mixed DSP and VHDL/Verilog etc. Environments 152
Embedded Processor-based Design Flows 153
Hard versus Soft Cores 155
Partitioning a Design into Its Hardware and Software Components 158
Using an FPGA as Its Own Development Environment 160
Improving Visibility in the Design 160
A Few Coverification Alternatives 161
Instant Summary 166
Chapter 7. Using Design Tools 168
Simulation Tools 169
Event-driven Logic Simulators 169
Logic Values and Different Logic Value Systems 171
Mixed-language Simulation 172
Alternative Delay Formats 173
Cycle-based Simulators 176
Choosing a Logic Simulator 178
Synthesis (Logic/HDL versus Physically Aware) 179
Logic/HDL Synthesis Technology 179
Physically Aware Synthesis Technology 180
Retiming, Replication, and Resynthesis 181
Timing Analysis 182
Static Timing Analysis 182
Statistical Static Timing Analysis 183
Verification in General 184
Verification IP 184
Verification Environments and Creating Testbenches 186
Analyzing Simulation Results 187
Formal Verification 187
Different Flavors of Formal Verification 187
Terminology and Definitions 189
Alternative Assertion/Property Specification Techniques 191
Static Formal versus Dynamic Formal 192
Miscellaneous 195
HDL to C Conversion 195
Code Coverage 195
Performance Analysis 196
Instant Summary 197
Chapter 8. Choosing the Right Device 198
Choosing 198
Technology 200
Basic Resources and Packaging 200
General-purpose I/O Interfaces 201
Embedded Multipliers, RAMs, etc. 201
Embedded Processor Cores 202
Gigabit I/O Capabilities 202
IP Availability 202
Speed Grades 203
Future FPGA Developments 204
Instant Summary 209
Index 210
A 210
B 211
C 211
D 212
E 213
F 213
G 214
H 214
I 214
J 214
L 214
M 215
N 215
O 215
P 215
Q 216
R 216
S 216
T 217
U 217
V 217
W 217
X 217

Produkt-Details

• Erscheint lt. Verlag: 8.4.2011
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• ISBN-10: 0-08-056011-3 / 0080560113
• ISBN-13: 978-0-08-056011-3 / 9780080560113