Design for Manufacturability and Yield for Nano-Scale CMOS (eBook)

Charles Chiang, Jamil Kawa (Autoren)

eBook Download: PDF

2007 | 2007
XXVII, 255 Seiten
Springer Netherland (Verlag)
978-1-4020-5188-3 (ISBN)

Infos

This book walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process. It covers all CAD/CAE aspects of a SOC design flow and addresses a new topic (DFM/DFY) critical at 90 nm and beyond. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.

Dr. Charles Chiang is R&D Director of the Advanced Technology Group at Synopsys Inc. in Mountain View, CA, USA

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Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design's manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.

Inhalt

1. Introduction of DFM/DFY. a. What is DFM/DFY ? historical perspective. b. Why is it becoming ever so critical? c. DFM categories & classifications. d. How do various DFM solutions tie up with specific design flows. e. DFM & DFY are intertwined. 2. Random Defects. a. CAA. b. Improving CAA. c. Cell library yield grading based on CAA. 3. Systematic yield. a. Lithography. 4. Systematic yield. b. CMP 5. Parametric yield. a. Intro. b. Timing aspects. c. Power considerations. 6. Design for yield. a. analysis. b. prediction. c. enhancement. 7. Summary and Conclusions

Produkt-Details

• Erscheint lt. Verlag: 15.6.2007
• Reihe/Serie: Integrated Circuits and Systems
• Reihe/Serie: Integrated Circuits and Systems
• Zusatzinfo: XXVII, 255 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Software Entwicklung
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: CAD (Computer aided design) • CAE (Computer aided engineering) • classification • CMOS • Computer Aided Design • Computer-Aided Design (CAD) • Computer Aided Engineering • Computer-Aided Engineering (CAE) • Design • Design for manufacturability) • Design for yield • Development • Integrated circuit • Layout • Model • nano-scale • Simulation • Standard • System on a chip design • Tables
• ISBN-10: 1-4020-5188-3 / 1402051883
• ISBN-13: 978-1-4020-5188-3 / 9781402051883