Run-time Adaptation for Reconfigurable Embedded Processors (eBook)

Lars Bauer, Jörg Henkel (Autoren)

eBook Download: PDF

2010 | 2011
XXI, 223 Seiten
Springer New York (Verlag)
978-1-4419-7412-9 (ISBN)

Infos

Embedded processors are the heart of embedded systems. Reconfigurable embedded processors comprise an extended instruction set that is implemented using a reconfigurable fabric (similar to a field-programmable gate array, FPGA). This book presents novel concepts, strategies, and implementations to increase the run-time adaptivity of reconfigurable embedded processors. Concepts and techniques are presented in an accessible, yet rigorous context. A complex, realistic H.264 video encoder application with a high demand for adaptivity is presented and used as an example for motivation throughout the book. A novel, run-time system is demonstrated to exploit the potential for adaptivity and particular approaches/algorithms are presented to implement it.

Inhalt

Run-time Adaptation for Reconfigurable Embedded Processors 3
Contents 5
Abbreviations 9
List of Figures 13
List of Tables 19
List of Algorithms 21
Chapter 1: Introduction 22
1.1 Application-Specific Instruction Set Processors 23
1.2 Reconfigurable Processors 24
1.2.1 Summary of Reconfigurable Processors 25
1.3 Contribution of this Monograph 26
1.4 Monograph Outline 27
Chapter 2: Background and Related Work 29
2.1 Extensible Processors 29
2.2 Reconfigurable Processors 31
2.2.1 Granularity of the Reconfigurable Fabric 31
2.2.2 Using and Partitioning the Reconfigurable Area 37
2.2.3 Coupling Accelerators and the Processor 41
2.2.4 Reconfigurable Instruction Set Processors 43
2.3 Summary of Related Work 46
Chapter 3: Modular Special Instructions 48
3.1 Problems of State-of-the-Art Monolithic Special Instructions 48
3.2 Hierarchical Special Instruction Composition 53
3.3 Example Special Instructions for the ITU-T H.264 Video Encoder Application 60
3.4 Formal Representation and Combination of Modular Special Instructions 68
3.5 Summary of Modular Special Instructions 72
Chapter 4: The RISPP Run-Time System 74
4.1 RISPP Architecture Overview 74
4.1.1 Summary of the RISPP Architecture Overview 77
4.2 Requirement Analysis and Overview 77
4.2.1 Summary of the Requirement Analysis and Overview 84
4.3 Online Monitoring and Special Instruction Forecasting 85
4.3.1 Fine-Tuning the Forecast Values 88
4.3.2 Evaluation of Forecast Fine-Tuning 92
4.3.3 Hardware Implementation for Fine-Tuning the Forecast Values 95
4.3.4 Summary of the Online Monitoring and SI Forecasting 98
4.4 Molecule Selection 99
4.4.1 Problem Description for Molecule Selection 100
4.4.2 Parameter Identification for the Profit Function 103
4.4.3 Heuristic Solution for the Molecule Selection 106
4.4.4 Evaluation and Results for the Molecule Selection 109
4.4.5 Summary of the Molecule Selection 115
4.5 Reconfiguration-Sequence Scheduling 116
4.5.1 Problem Description for Reconfiguration-Sequence Scheduling 117
4.5.2 Determining the Molecule Reconfiguration Sequence 120
4.5.3 Evaluation and Results for the Reconfiguration-Sequence Scheduling 125
4.5.4 Summary of the Reconfiguration-Sequence Scheduling 128
4.6 Atom Replacement 129
4.6.1 Motivation and Problem Description of State-of-the-Art Replacement Policies 129
4.6.2 The MinDeg Replacement Policy 133
4.6.3 Evaluation and Results 136
4.6.4 Summary of the Atom Replacement 141
4.7 Summary of the RISPP Run-Time System 142
Chapter 5: RISPP Architecture Details 144
5.1 Special Instructions as Interface Between Hardware and Software 145
5.2 Executing Special Instructions Using the Core Instruction Set Architecture 150
5.3 Data Memory Access for Special Instructions 155
5.4 Atom Infrastructure 158
5.4.1 Atom Containers and Bus Connectors 162
5.4.2 Load/Store- and Address Generation Units 167
5.4.3 Summary of the Atom Infrastructure 171
5.5 RISPP Prototype Implementation and Results 171
5.6 Summary of the RISPP Architecture Details 182
Chapter 6: Benchmarks and Comparisons 183
6.1 Benchmarking the RISPP Approach for Different Architectural Parameters 184
6.2 Comparing Different Architectures 187
6.2.1 Assumptions and Similarities 188
6.2.2 Dissimilarities 189
6.2.3 Fairness of Comparison 190
6.2.4 Summary of Comparing Different Architectures 191
6.3 Comparing RISPP with Application-Specific Instruction Set Processors 192
6.4 Comparing RISPP with Reconfigurable Processors 200
6.5 Summary of Benchmarks and Comparisons 205
Chapter 7: Conclusion and Outlook 208
7.1 Summary 208
7.2 Future Work 210
Appendix A: RISPP Simulation 213
Appendix B: RISPP Prototype 220
Bibliography 225
Index 234

Produkt-Details

• Erscheint lt. Verlag: 1.12.2010
• Zusatzinfo: XXI, 223 p.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: ASIP • design automation • embedded processors • Embedded Systems • FPGA • reconfigurable computing • Reconfigurable embedded processors • Reconfigurable Processors
• ISBN-10: 1-4419-7412-1 / 1441974121
• ISBN-13: 978-1-4419-7412-9 / 9781441974129