Ultra-thin Chip Technology and Applications (eBook)

Joachim Burghartz (Herausgeber)

eBook Download: PDF

2010 | 2011
XXII, 467 Seiten
Springer New York (Verlag)
978-1-4419-7276-7 (ISBN)

Infos

Ultra-thin chips are the 'smart skin' of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, Microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

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Ultra-thin chips are the "e;smart skin"e; of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, Microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

Inhalt

Preface 8
Contents 12
About the Editor 16
Contributors 18
Part I: From Thick Wafers to Ultra-Thin Silicon Chips 24
Chapter 1: Why Are Silicon Wafers as Thick as They Are? 25
1.1 Moore´s Law and Trend in Wafer Diameter 25
1.2 Wafer Size and Wafer Thickness 26
1.3 Silicon Wafer and Its Defect Kinetic Properties 29
1.4 More than Moore Applications 31
References 33
Chapter 2: Thin Chips on the ITRS Roadmap 35
2.1 The ITRS Roadmap 35
2.2 Thin Chips for More Moore 36
2.3 Thin Chips for More than Moore 38
References 40
Part II: Thin Chip Fabrication Technologies 41
Chapter 3: Thin Wafer Manufacturing and Handling Using Low Cost Carriers 43
3.1 Wafer Thinning Technologies for Different Thickness Ranges 43
3.2 Thinned Wafer Properties 45
3.3 Impact of Wafer Frontside Design 47
3.4 Wafer Thinning Under Economic Constraints 52
References 54
Chapter 4: Ultra-thin Wafer Fabrication Through Dicing-by-Thinning 55
4.1 Challenges in Thin Wafer Fabrication 55
4.2 Dicing-by-Thinning Concept 56
4.3 Plasma Trench Etching for Die Separation 58
4.4 Combination of Sawing and Plasma Etching for Die Separation 60
4.5 Ultra-thin RFID Devices Prepared Through Dicing-by-Thinning 61
4.6 Outlook: Self-assembly of Ultra-thin RFID Devices 63
References 64
Chapter 5: Thin Wafer Handling and Processing without Carrier Substrates 66
5.1 Issues with Wafer Thinning 66
5.1.1 Reduction in Wafer Rigidity (Warpage, Deflection) 66
5.1.2 Grinding Damage 67
5.1.3 Wafer Edge Chipping 67
5.1.4 Wafer Dicing 68
5.2 DBG (Dicing-Before-Grinding) Process 68
5.3 TAIKO Process 70
5.4 Conclusions 72
Chapter 6: Epitaxial Growth and Selective Etching Techniques 73
6.1 Process Overview 73
6.1.1 Selective Wet Chemical Etching of Si 74
6.1.2 Highly Boron-Doped Si Epitaxy on Low-Doped Substrates 76
6.2 Process Results 77
References 80
Chapter 7: Silicon-on-Insulator (SOI) Wafer-Based Thin-Chip Fabrication 81
7.1 SOI Technologies 81
7.1.1 History of SOI Wafer Technology 82
7.1.2 Classification of SOI Wafer Fabrication 82
7.2 SOI-Based Thin-Chip Fabrication 85
References 87
Chapter 8: Fabrication of Ultra-thin Chips Using Silicon Wafers with Buried Cavities 88
8.1 The Chipfilm Concept 88
8.2 The Pre-process Module Chipfilm 89
8.3 CMOS Circuit Integration on Chipfilm Wafers 93
8.4 The Pick, CrackandPlaceTM Post-process 93
8.5 Characterisation of Chipfilm Dies 94
References 96
Part III: Add-on Processing 97
Chapter 9: Through-Silicon Vias Using Bosch DRIE Process Technology 99
9.1 Silicon Plasma Etching: Fundamentals on Etching Equipment and Processes 99
9.1.1 High-Density Plasma Sources 101
9.1.2 The Bosch Process: Repetitive Cycling of Passivation and Etching Steps 101
9.2 The Bosch Process: Characteristics and Effects Relevant for Through-Silicon Via Applications 103
9.2.1 Solutions for Reduction of Sidewall Scalloping for TSVs 104
9.2.2 The Notching Phenomenon: Its Relevance to TSV Etching and Solutions to Overcome Notching 105
9.2.3 Parameter Ramping for High-Aspect Ratio TSV Etching 107
9.3 Summary and Conclusions 108
References 109
Chapter 10: Through-Silicon via Technology for 3D IC 110
10.1 Introduction 110
10.1.1 3D Interconnect Hierarchy 110
10.1.2 Classification of 3D Interconnect Hierarchy 111
10.1.3 3D Process Options Using Through-Si Via Technology 113
10.2 Through-Silicon via and 3D Stacking Technology 116
10.2.1 Introduction 116
10.2.2 TSV Hole Formation 116
10.2.3 TSV Isolation Liner Process 118
10.2.4 TSV Barrier Layer 118
10.2.5 TSV Metal Fill Process 119
10.2.5.1 Cu-TSV 119
10.2.5.2 W-TSV 120
10.2.5.3 Poly-Si TSV 121
10.3 Wafer Thinning and Backside Processing 122
10.3.1 Wafer Thinning and Backside Processing for TSV Before 3D Stacking 122
10.3.2 Wafer Thinning and Backside Processing for TSV after 3D Stacking 124
10.4 Stacking Technology Module 124
References 124
Chapter 11: 3D-IC Technology Using Ultra-Thin Chips 126
11.1 Introduction 126
11.2 3D Integration by Wafer-to-Wafer Bonding 127
11.3 3D Integration by Chip-to-Wafer Bonding 130
11.4 3D Integration by Multichip-to-Wafer Bonding 132
11.5 3D Integration by Reconfigured Wafer-to-Wafer Bonding 135
11.6 3D-IC Test Chip Fabrication 136
11.7 Concerns in 3D Integration Using Ultra-Thin Chips 138
References 140
Chapter 12: Substrate Handling Techniques for Thin Wafer Processing 141
12.1 Need for Support: Thinner Devices in Semiconductor Industry 141
12.2 General Requirements 142
12.3 Overview on Temporary Bonding Techniques 145
12.4 Thermoplastic Materials 145
12.5 Debonding After Laser Treatment 146
12.6 Soluble Bonding Materials 146
12.7 Reversible Adhesive Tapes 147
12.8 Mechanical Debonding 148
12.9 Electrostatic Bonding 149
12.10 Thin Die Handling 151
12.11 Comparison of Different Carrier Techniques 152
References 153
Part IV: Assembly and Embedding of Ultra-Thin Chips 155
Chapter 13: System-in-Foil Technology 157
13.1 Introduction 157
13.2 Concept, Materials and Processes 158
13.3 Embedding of Chips 160
13.3.1 Ultra-thin Chip Package (UTCP) 160
13.3.2 Embedded Circuitry for Ultra-thin Chip Assembly 163
13.3.3 Embedded Optical Chips 166
13.4 Applications 169
13.5 Conclusion and Summary 172
References 173
Chapter 14: Chip Embedding in Laminates 174
14.1 Introduction 174
14.2 Concepts for Embedding Chips in PWB 175
14.3 Realisation of Embedded Technology in the Production Process: A Practical Approach 177
14.4 Outlook: Flexible Systems with Embedded Actives 179
References 180
Chapter 15: Handling of Thin Dies with Emphasis on Chip-to-Wafer Bonding 181
15.1 Introduction to the Die Bonding Process 181
15.1.1 Direct Die Placement 182
15.1.2 Flip Chip Placement 184
15.2 From Thick Die to Thin Die 184
15.2.1 Die Pickup from Wafer Tape 187
15.2.1.1 Wafer to Ejector Angular Alignment 187
15.2.1.2 Visual Die Alignment 187
15.2.1.3 Die Ejection 187
15.2.2 Die Transfer 189
15.2.2.1 Pickup Tools 189
15.2.2.2 Visual Die Alignment 190
15.2.3 Die Placement 191
15.3 Application Examples 192
15.3.1 Embedded Thin Dies 193
15.3.2 Chip-to-Wafer 195
References 197
Chapter 16: Micro Bump Assembly 198
16.1 Introduction 198
16.1.1 Micro Bump Formation 199
16.1.2 Metallurgical Fundamentals for Micro Bump Assembly 200
16.2 Micro Bump Joining Methods 202
16.2.1 Reflow Solder Joining 202
16.2.2 Thermo-compression Joining 202
16.2.3 Underfill Integration 203
16.3 Micro Bump Stacking Approaches 204
References 205
Part V: Characterization and Modelling 206
Chapter 17: Mechanical Characterisation and Modelling of Thin Chips 207
17.1 Fracture and Strength of Brittle Materials 207
17.2 Strength Issues in Silicon Chip Manufacturing 212
17.3 Strength Testing Methods for Thin Samples 213
17.3.1 Uniaxial Bending Tests 214
17.3.2 Biaxial Bending Tests 217
17.3.3 Statistical Evaluation 220
17.3.4 Importance of Considering Nonlinearities 222
17.4 Examples of Strength of Thin Chips 223
17.4.1 Strength of Chips Edges: Dicing Technologies 223
17.4.2 Strength of Chip Surface: Grinding Technologies 226
17.5 Conclusions 227
References 228
Chapter 18: Structure Impaired Mechanical Stability of Ultra-thin Chips 231
18.1 Concepts 231
18.2 Experimental Methodologies to Examine Structure Impaired Mechanical Stability of Ultra-thin Chips 232
18.2.1 ChipfilmTM Process and Sample Preparations 233
18.2.2 3-Point Bending Test 234
18.2.3 Weibull Statistics and FEM Analysis 235
18.3 Experimental Results and Discussions 237
18.3.1 Evaluation of Anchor Effects on Chip´s Mechanical Strength 238
18.3.2 Evaluation of Influences of the Porous Silicon Layer 240
18.3.3 Evaluation Effects of Ultra-thin IC Chips 242
18.4 Conclusions 243
References 243
Chapter 19: Piezoresistive Effect in MOSFETS 245
19.1 Strain Effects: From Si to MOSFETs 245
19.1.1 Stress and Strain 246
19.1.2 Strain-Induced Enhancement of Si Electron Mobility 247
19.1.3 Strain-Induced Enhancement of Si Hole Mobility 248
19.1.4 Transport Properties in Strained Si 249
19.2 Strain-Induced Effects in MOSFETs 250
19.3 Conclusion 254
References 254
Chapter 20: Electrical Device Characterisation on Ultra-thin Chips 256
20.1 Introduction 256
20.2 Bending Techniques 257
20.3 Measurement Techniques 259
20.3.1 Temperature Effect 261
20.4 Evaluation of Measurement Data 262
20.5 Conclusions 267
References 267
Chapter 21: MOS Compact Modelling for Flexible Electronics 269
21.1 Introduction 269
21.2 The State of the Art in MOS Compact Modelling 270
21.3 Strain Considerations in Flexible Electronics 272
21.4 Modelling of General Strain Effects on Band Edge Energies 274
21.5 Modelling of General Strain Effects on Channel Mobility 276
21.6 Compact Model Implementation 278
References 279
Chapter 22: Piezojunction Effect: Stress Influence on Bipolar Transistors 281
22.1 Introduction 281
22.2 Current-Voltage Characteristics 282
22.3 Charge Transport Parameters 284
22.4 Piezoresistance and Piezojunction Coefficients 285
22.5 Use of the Model for Design Purposes 288
22.6 Conductivity Calculations from First Principles 290
22.7 Conclusions 293
References 294
Chapter 23: Thermal Effects in Thin Silicon Dies: Simulation and Modelling 296
23.1 Introduction 296
23.2 Numerical Analysis of UTCS Modules 297
23.2.1 Single-Level Module 297
23.2.2 Two-Level Module 303
23.2.3 Three-Level Module 305
23.3 Thermal Modelling of UTCS Modules 310
23.3.1 Compact Thermal Models: A Perspective 310
23.3.2 Compact Thermal Model Formulation 311
23.3.2.1 Junction Temperature Equation 314
23.3.2.2 Boundary Heat Flux Equations 314
23.3.2.3 Constraint Relations 314
References 317
Chapter 24: Optical Characterisation of Thin Silicon 318
24.1 Introduction 318
24.2 Light Trapping 319
24.3 Maximum Efficiency of Thin Crystalline Silicon Solar Cells 319
24.4 Vertical and Lateral Solar Cell Designs 321
24.5 Laser Doping of p- and n-Type Areas 323
24.6 Quantum Efficiency 324
References 326
Part VI: Applications 328
Chapter 25: Thin Chips for Power Applications 330
25.1 Low Voltage MOSFETs 330
25.1.1 IGBTs and FWDs 335
25.2 Influence of Thin Wafers on Product Definition and Application 339
25.2.1 Thermal and Electrical Aspects 339
25.2.2 Alternative Packaging Methods Enabled by Thin Wafer Technologies 342
References 343
Chapter 26: Thinned Backside-Illuminated (BSI) Imagers 345
26.1 Introduction 345
26.1.1 Detecting Light 345
26.1.2 Limitations of Frontside Illumination 346
26.1.3 Backside Illumination 346
26.1.4 Relation Between QE, Crosstalk and Substrate Thickness 347
26.1.5 Imager Types and Roadmap 348
26.2 Specific Hybrid BSI CMOS Imager Technologies 349
26.2.1 Substrate Engineering 350
26.2.2 Trench Formation 350
26.2.3 Wafer Thinning and Handling 351
26.2.4 Backside Surface Treatment 352
26.2.5 Anti-reflective Coating 353
26.2.6 Hybrid Integration 354
26.3 Results of IMEC-Thinned BSI Imagers 355
26.3.1 Functionality and Yield 355
26.3.2 Dark Current 355
26.3.3 Quantum Efficiency 356
26.3.4 Crosstalk 357
References 360
Chapter 27: Thin Solar Cells 361
27.1 Why Thin Solar Cells? 361
27.1.1 Less Material Consumption 362
27.1.2 Less Vulnerable to Low Bulk Carrier Lifetime 363
27.1.3 Higher Power Conversion Efficiency 364
27.1.4 Flexible Solar Cells 365
27.2 Overview on Thin Crystalline Silicon Solar Cells 365
27.2.1 Record Small Area Solar Cells 366
27.2.2 Thin Large Area Solar Cells 367
27.2.3 Thin Back Junction Back Contact Solar Cells 367
27.2.4 Overview on Thin Monocrystalline Silicon Solar Cells 368
27.3 Thin Solar Cell Applications 368
References 369
Chapter 28: Bendable Electronics for Retinal Implants 371
28.1 Introduction 371
28.1.1 Background 371
28.1.2 A Look Back 372
28.2 Implant Concepts and Techniques 372
28.2.1 Basic Implant Concepts 372
28.2.2 Electronic Design 374
28.3 Fabrication and Assembly of Retinal Implants 376
28.3.1 General Issues 376
28.3.2 Passive Sub-retinal Implants 378
28.3.3 Active Sub-retinal Implants 379
28.4 Summary 381
References 382
Chapter 29: Thin Chip Flow Sensors for Nonplanar Assembly 384
29.1 Introduction to Thermal Flow Sensors 384
29.2 Technological Approach 387
29.3 Sensor Characteristics 390
29.3.1 Electrical Characteristics 390
29.3.2 Flow Measurements 391
29.4 Conclusions and Outlook on Applications 392
References 393
Chapter 30: RFID Transponders 395
30.1 Overview 395
30.2 Applications 398
30.3 Ultra-thin RFID Transponders 399
30.4 RFID Transponders with On-Chip Antenna 401
30.5 Conclusion 402
References 403
Chapter 31: Thin Chips for Document Security 405
31.1 Ultra-Thin Chips - Enabler for Robust and Flexible RFID Applications 405
31.2 RFID Quality Requirements 407
31.3 Manufacturing Cost Reduction Stimulated by Thin Silicon 410
31.4 Thin Silicon Security Application Examples 412
31.4.1 Multifunctional Electronic Passports and ID Card 412
31.4.2 Display Card - A Multi-Chip SmartCard Application 413
31.4.3 Integration on Printed Inlays 414
31.4.4 Security Tags and Labels 415
31.4.5 Chip-in-Paper 416
31.4.6 Thin Components in Hybrid Systems 416
References 417
Chapter 32: Flexible Display Driver Chips 418
32.1 Introduction 418
32.2 Display Drivers 421
32.3 Ultra-Thin Driver Chips 422
References 427
Chapter 33: Microwave Passive Components in Thin Film Technology 430
33.1 Introduction 430
33.2 Spiral Inductors on Thin Chips 433
33.2.1 Electrical Parameters and the Equivalent Circuit Model 433
33.2.2 Numerical Experiments 435
33.3 Thin Chip Transmission Lines 441
33.3.1 Electrical Parameters and the Distributed Element Model 441
33.3.2 Numerical Results 442
33.3.2.1 CPW Transmission Lines 442
33.3.2.2 Microstrip Transmission Lines 445
33.4 Conclusion 447
References 448
Chapter 34: Through-Silicon via Technology for RF and Millimetre-Wave Applications 450
34.1 Grounded-TSV for RF Power Amplifiers 450
34.2 3D-IC Isolated TSV for High-Speed Applications 452
34.3 MMW Wilkinson Power Divider 455
34.4 Conclusions 457
References 458
Index 459

Produkt-Details

• Erscheint lt. Verlag: 18.11.2010
• Zusatzinfo: XXII, 468 p. 252 illus., 157 illus. in color.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Nachrichtentechnik
• Schlagworte: 3D Integrated Circuits • ChipFilm • Circuit Design • Embedded Systems • microelectronics • microsystems • nanomaterials • nanotechnology • System in Foil • Ultra-thin Chips
• ISBN-10: 1-4419-7276-5 / 1441972765
• ISBN-13: 978-1-4419-7276-7 / 9781441972767