Reliability of Nanoscale Circuits and Systems (eBook)

Methodologies and Circuit Architectures

Miloš Stanisavljević, Alexandre Schmid, Yusuf Leblebici (Autoren)

eBook Download: PDF

2010 | 2011
XXVII, 195 Seiten
Springer New York (Verlag)
978-1-4419-6217-1 (ISBN)

Infos

This book is intended to give a general overview of reliability, faults, fault models, nanotechnology, nanodevices, fault-tolerant architectures and reliability evaluation techniques. Additionally, the book provides an in depth state-of-the-art research results and methods for fault tolerance as well as the methodology for designing fault-tolerant systems out of highly unreliable components.

Miloš Stanisavljevic received the M.S. degree in electrical engineering from the Faculty of Electrical Engineering, University of Belgrade, Belgrade, Serbia, in 2004, and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 2009. During 2004, he was an Analog Design and Layout Engineer for Elsys Design, Belgrade/ Texas Instruments, Nice. In the end of 2004, he joined Microelectronic Systems Laboratory, EPFL, as a Research Assistant. During 2006, he was with International Business Machines Corporation (IBM) Research, Zurich, for six months, where he was involved in the project related to reliability emulation in the state-of-the-art nanoscale CMOS technology. He is currently engaged in the field of reliability and fault-tolerant design of nanometer-scale systems. His current research interests include mixed-signal gate and system level design, reliability evaluation, and optimization. Dr. Stanisavljevic received a Scholarship for Students with Extraordinary Results Awarded by the Serbian Ministry of Education from 1996 to 2004. Alexandre Schmid received the M.S. degree in Microengineering and the Ph.D. degree in Electrical Engineering from the Swiss Federal Institute of Technology (EPFL) in 1994 and 2000, respectively. He has been with the EPFL since 1994, working at the Integrated Systems Laboratory as a research and teaching assistant, and at the Electronics Laboratories as a post-doctoral fellow. He joined the Microelectronic Systems Laboratory in 2002 as a Senior Research Associate, where he has been conducting research in the fields of non-conventional signal processing hardware, nanoelectronic reliability, bioelectronic and brain-machine interfaces. Dr. Schmid has published over 70 peer-reviewed journal and conference papers. He has served in the conference committee of The International Conference on Nano-Networks since 2006, as technical program chair in 2008, and general chair in 2009. Dr. Schmid is an Associate Editor of the IEICE ELEX. Dr. Schmid is also teaching at the Microengineering and Electrical Engineering Departments/Sections of EPFL. Yusuf Leblebici received his B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, in 1984 and in 1986, respectively, and his Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990. Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI). In 2000-2001, he also served as the Microelectronics Program Coordinator at Sabanci University. Since 2002, Dr. Leblebici has been a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is the coauthor of 4 textbooks, namely, Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer Academic Publishers, 1993), CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 1st Edition 1996, 2nd Edition 1998, 3rd Edition 2002), CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Springer, 2007) and Fundamentals of High Frequency CMOS Analog Integrated Circuits (Cambridge University Press, 2009), as well as more than 200 articles published in various journals and conferences. He has served as an Associate Editor of IEEE Transactions on Circuits and Systems (II), and IEEE Transactions on Very Large Scale Integrated (VLSI) Systems. He has also served as the general co-chair of the 2006 European Solid-State Circuits Conference, and the 2006 European Solid State Device Research Conference (ESSCIRC/ESSDERC). He is a Fellow of IEEE and has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.

Inhalt

Preface 6
Acknowledgments 9
About the Authors 10
Contents 12
List of Figures 15
List of Tables 19
Acronyms 21
1 Introduction 24
1.1 From Microelectronics to Nanoelectronics 24
1.2 Issues Related to Reliable Design 28
1.3 Outline of the Book 29
2 Reliability, Faults, and Fault Tolerance 30
2.1 Reliability and FaultTolerance 30
2.2 Faults and Fault Models 33
2.3 Transistor Fault Model 36
3 Nanotechnology and Nanodevices 42
3.1 Single-Electron Transistors (SETs) 44
3.2 Resonant Tunneling Devices (RTDs) 46
3.3 Quantum Cellular Automata (QCA) 47
3.4 One-Dimensional (1D) Devices 48
3.5 CMOS-Molecular Electronics (CMOL) 50
3.6 Other Nanoelectronic Devices 51
3.7 Overview of Nanodevices' Characteristics 52
3.8 Challenges for Designing System Architectures Based on Nanoelectronic Devices 55
4 Fault-Tolerant Architectures and Approaches 58
4.1 Static Redundancy 59
4.1.1 Hardware Redundancy 59
4.1.2 Time Redundancy 64
4.1.3 Information Redundancy 64
4.1.4 Hybrid Approaches 65
4.1.5 Recent Techniques 66
4.2 Dynamic Redundancy 66
4.2.1 Reconfiguration 67
4.3 Overview of the Presented Fault-Tolerant Techniques 69
5 Reliability Evaluation Techniques 71
5.1 Historically Important Tools 73
5.2 Most Recent Progress in Reliability Evaluation 75
5.3 Monte Carlo Reliability Evaluation Tool 79
5.4 Summary 83
6 Averaging Design Implementations 84
6.1 The Averaging Technique 84
6.1.1 Feed-Forward ANN Boolean Function Synthesis Block 85
6.1.2 Four-Layer Reliable Architecture (4LRA) 87
6.1.3 Hardware Realizations of Averaging and Thresholding 89
6.1.4 Examples of Four-Layer Reliable ArchitectureTransfer Function Surfaces 91
6.2 Assessment of the Reliability of Gates and Small Blocks 97
6.2.1 Comparative Analysis of Obtained Results 98
6.3 Differential Signaling for Reliability Improvement 102
6.3.1 Fault-Tolerant Properties of Differential Signaling 102
6.3.2 Comparative Analysis of Obtained Results 103
6.4 Reliability of SET Systems 106
6.4.1 Reliability Evaluation 107
6.4.2 Comparison of Different Fault-Tolerant Techniques 110
6.5 Summary 113
7 Statistical Evaluation of FaultTolerance Using Probability Density Functions 114
7.1 Statistical Method for the Analysis of Fault-Tolerant Techniques 115
7.2 Advanced Single-Pass Reliability Evaluation Method 124
7.2.1 Modified Single-Pass Reliability Evaluation Tool 125
7.2.2 Output PDF Modeling 133
7.3 Conclusions 139
8 Design Methodology: Reliability Evaluationand Optimization 141
8.1 Local-Level Reliability Evaluation 143
8.1.1 Dependency of Reliability on Logic Depth 145
8.1.2 Reliability Improvement by Logic Depth Reduction 147
8.1.3 Reliability Improvement of Different Fault-Tolerant Techniques 148
8.2 Optimal Reliability Partitioning 154
8.2.1 Partitioning to Small and Mid-Sized Partitions 156
8.2.2 Partitioning to Large-Sized Partitions 158
8.3 System-Level Evaluation and Optimization 159
8.3.1 R-Fold Modular Redundancy (RMR) 165
8.3.2 Cascaded R-Fold Modular Redundancy (CRMR) 171
8.3.3 Distributed R-Fold Modular Redundancy (DRMR) 175
8.3.4 NAND Multiplexing 181
8.3.5 Chip-Level Analysis 183
8.4 Conclusions 185
9 Summary and Conclusions 187
9.1 Reliability-Aware Design Methodology 187
9.2 Conclusions or Back into the Big Picture 189
A Probability of Chip and Signal Failurein System-Level Optimizations 191
A.1 Probability of Chip Failure for Cascaded R-Fold Modular Redundancy Architecture 191
A.1.1 Generalization 194
A.2 Probability of Input Signals Failure in Distributed R-Fold Modular Redundancy Architecture 195
References 197
Index 211

Produkt-Details

• Erscheint lt. Verlag: 20.10.2010
• Zusatzinfo: XXVII, 195 p.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Technik ► Bauwesen
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Maschinenbau
• Themenwelt: Wirtschaft ► Betriebswirtschaft / Management
• Schlagworte: Averaging Design Implementations • Fault Models • faults • Fault-Tolerant Approaches • fault-tolerant architectures • Nanodevices • nanotechnology • Quality Control, Reliability, Safety and Risk • Reliability • Reliability Evaluation Techniques • Statistical Evaluation of Fault-Tolerance Using Probabil • Statistical Evaluation of Fault-Tolerance Using Probability • System Level Reliability Evaluation and Optimization
• ISBN-10: 1-4419-6217-4 / 1441962174
• ISBN-13: 978-1-4419-6217-1 / 9781441962171