Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s (eBook)

Selected Contributions on Specification, Design, and Verification from FDL 2009

Dominique Borrione (Herausgeber)

eBook Download: PDF

2010 | 2010
VIII, 248 Seiten
Springer Netherland (Verlag)
978-90-481-9304-2 (ISBN)

Infos

More than ever, FDL is the place for researchers, developers, industry designers, academia, and EDA tool companies to present and to learn about the latest scientific achievements, practical applications and users experiences in the domain of specification and design languages. FDL covers the modeling and design methods, and their latest supporting tools, for complex embedded systems, systems on chip, and heterogeneous systems.

FDL 2009 is the twelfth in a series of events that were held all over Europe, in selected locations renowned for their Universities and Reseach Institutions as well as the importance of their industrial environment in Computer Science and Micro-electronics. In 2009, FDL was organized in the attractive south of France area of Sophia Antipolis. together with the DASIP (Design and Architectures for Signal and Image Processing) Conference and the SAME (Sophia Antipolis MicroElectronics ) Forum.

All submitted papers were carefully reviewed to build a program with 27 full and 10 short contributions. From these, the Program Committee selected a shorter list, based on the evaluations of the reviewers, and the originality and relevance of the work that was presented at the Forum. The revised, and sometimes extended versions of these contributions constitute the chapters of this volume.

Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's presents extensions to standard specification and description languages, as well as new language-based design techniques and methodologies to solve the challenges raised by mixed signal and multi-processor systems on a chip. It is intended as a reference for researchers and lecturers, as well as a state of the art milestone for designers and CAD developers.

Inhalt

Preface 6
Contents 8
Part I UML and MDE for Embedded Systems 10
Chapter 1:IP-XACT Components with Abstract Time Characterization 11
1. Introduction 11
2. Related Work 14
3. MARTE CCSL 14
4. Example -- AHB to APB Bridge 15
Informal Specification 16
CCSL Specification 17
5. Comparing RTL and TLM Implementations 21
6. Conclusions 23
References 24
Chapter 2:MDE Support for HW/SW Codesign: A UML-based Design Flow 27
1. Introduction 27
2. State-of-the-Art and Related Works 29
Hardware/Software Co-design 30
Related Work 32
3. Theoretical Context 33
4. Codesign-Driven Modeling: Integrated Design Flow 34
Design Rules 35
Mathematical Formalization and MARTE 36
Co-design Analysis 37
5. Code Generation: from MARTE Models to SystemC 38
Architectural Extensions 39
Translation Rules 40
6. Case Study 40
7. Conclusions and Future Works 42
References 43
Part II C/C++-Based System Design 46
Chapter 3:Checkpoint and Restore for SystemC Models 48
1. Introduction 49
Checkpointing Implementation Issues 50
2. Simics Checkpointing Basics 51
3. SystemC in Simics 53
4. Checkpointing SystemC Model State 54
Model Requirements 54
SystemC Parameters to Simics Attributes 54
Limitations 55
5. Checkpointing SystemC Kernel State 56
6. Related Work 57
7. Experiments 58
Simics-SystemC Bridge Performance 58
SystemC Checkpoint Support Overhead 59
Validating Basic Checkpointing 59
Validating Model Updates 60
Checkpoint Size 60
Complex Test Case 61
8. Discussion 62
9. Conclusions 63
References 63
Chspter 4:Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs 65
1. Introduction 65
2. Related Work 67
3. Temporal Abstraction Levels 69
4. Modeling 70
Application Modeling 70
Modeling MPSoC Architectures 71
Setting the Mapping Constraints 72
5. Performance Evaluation 73
Activation-Based Execution 73
Transaction-Based Communication 74
Performance Evaluation 75
6. Case Study: Motion-JPEG Decoder 76
Design Space Exploration 76
Transaction Delays 76
7. Conclusions 77
References 77
Chapter 5: Fast SystemC Performance Models for the Exploration of Embedded Memories 79
1. Introduction 79
2. The Memory Design Space 81
3. Related Work 81
4. Exploration Framework 82
Representation of Data and Storage 83
Performance Simulation 83
Analysis of a Memory Hierarchy 84
5. Memory Models 85
Single Access Model 86
Grouped Access Model 86
Iterated Contention Algorithm 88
6. Quality of Memory Models 89
Impact of Access Distributions 89
Comparison of Access Models 90
Accuracy of Access Models 91
Simulation Performance 93
7. Case Study 94
Impact of Memory Subsystem 94
Application and Memory Mappings 94
Discussion 96
8. Conclusion 97
Acknowledgment 97
References 97
Chapter 6:Another Take on Functional System-Level Design and Modeling 99
1. Introduction 99
2. State of the Art 100
3. Overview 101
Engine/MoC Dichotomy 101
Data Exchange Between MoCs 102
MoC Design 102
Engine Design 103
4. Examples 104
Instrumentation 104
Evaluation of Memory Access Costs for Tomographic Reconstruction 106
Cache Memory Models 106
User Specified Design 106
Performance Discussion 108
5. Conclusion 111
References 111
Chapter 7:Design Automation Model for Application-Specific Processors on Reconfigurable Fabric 113
1. Introduction 113
2. Languages for Customizable Processors 115
3. RH(+) Model 116
Abstraction of Low-Level Details for Instruction Set 116
Flexible Operator Definition 117
Flexible Data Types 118
Configurability and Self-Retargettable Compiler 119
Constraints Setting 119
4. Implementation of RH(+) 119
FRH(+) 120
LRH(+) 121
Constraints and Configurability 122
Instruction Selection and Generation 123
Compiler 124
5. Illustrative Example 125
6. Conclusions and Future Work 129
Acknowledgment 129
References 129
Chspter 8: A SystemC Superset for High-Level Synthesis 131
1. Introduction 131
2. SystemC Synthesizable Superset 133
HLS Modules 133
HLS Interfaces 134
Interface Object Types 135
HLS Threads 136
HLS Shared Variables 137
Schedule Object and Timing Annotation Points 137
3. Timing Accuracy Levels 139
Approximately-Timed Simulation Mode 139
Cycle-Accurate at the Transactions Boundaries (CATB) Simulation Mode 139
Loosely-Timed Simulation Mode 139
Un-timed Simulation Mode 140
4. Design Flow 140
5. Results 140
6. Conclusions 143
References 143
Part III Embedded Analog and Mixed-Signal System Design 145
Chapter 9:Design of Experiments for Effective Pre-silicon Verification of Automotive Electronics 146
1. Introduction 146
2. State of the Art 147
3. Design of Experiments 149
4. Approach 150
Objective 150
Abstract Description 151
Implementation 153
5. Results 154
System Overview 154
Implementation 155
(1) System Monte Carlo (MC) 156
(2) Two-Level Full Factorial (DoE1) 158
(3) Multi-level Full Factorial (DoE2) 158
(4) Response Surface DoE -- CCD (DoE3) 160
Discussion 161
6. Conclusion 162
Acknowledgement 162
References 163
Chspter 10:A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems 164
1. Introduction 165
2. Modeling Methodology 167
Specifications for the Frequency Synthesizer 168
Design, Implementation, and Test of the Frequency Synthesizer 173
3. Usage of the RF_TRX Library in the Design Process of a Binary FSK Transmitter 177
Implementation of the FSK Transmitter Model 177
Simulation of Different Transmitter Design Cases 178
4. Conclusions and Outlook 182
Acknowledgment 183
References 183
Part IV Assertion Based Design, Verification & Debug
Chspter 11:High Level Synthesis Using Operation Properties 186
1. Introduction 186
2. Previous Work 187
3. Operation Properties 188
4. Synthesis Algorithm 190
5. Results 195
6. Conclusion 196
References 196
Chapter 12:A Re-Use Methodology for Formal SoC Protocol Compliance Verification 199
1. Introduction 200
2. Verification Methodology 202
3. Formal Protocol Specification 204
Bus Recorder 204
Properties 208
4. Experimental Results 210
Recorder Versus Monitor 210
Checking Protocol Compliance with Standard Property Checking Techniques 211
Checking Protocol Compliance Using IPC and Reachability Analysis 211
Reachability Analysis 211
Verifying Properties Using IPC 212
5. Conclusion 213
References 213
Chapter 13:ISIS: Runtime Verification of TLM Platforms 215
1. Introduction 215
2. A Framework for the ABV of TLM Models 216
Monitoring TLM Descriptions -- Principles 217
Discussion About the ``Next' Operator 218
3. Using the Boolean and Modeling Layers 218
Boolean Layer: C++ Predicates 218
Modeling Layer: Auxiliary Variables 219
4. The ISIS Tool 220
5. Experimental Results 221
Producers/Consumer with a FIFO Channel 222
DMA System 223
Protocol over Faulty Channel 224
Packet Switch 225
Motion-JPEG Case Study 225
6. Related Work 226
7. Conclusion 227
Notes 227
References 227
Chapter 14:SMT-based Stimuli Generation in the SystemC Verification Library 229
1. Introduction 229
2. Preliminaries 231
SystemC Verification Library 231
SAT Modulo Theory 232
3. SMT-Based Stimuli Generation 233
Limits of BDDs 233
Integrating SAT Modulo Theories 234
4. Distribution of Generated Stimuli 236
Determine Distributed Solutions 236
Choosing Solutions 238
Handling Overconstraining 239
5. Experimental Evaluation 239
6. Conclusions and Future Work 243
Notes 244
References 244
Index 247

Produkt-Details

• Erscheint lt. Verlag: 24.8.2010
• Reihe/Serie: Lecture Notes in Electrical Engineering
• Reihe/Serie: Lecture Notes in Electrical Engineering
• Zusatzinfo: VIII, 248 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge
• Themenwelt: Informatik ► Theorie / Studium ► Compilerbau
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Nachrichtentechnik
• Schlagworte: Assertion Based Design & Verification • C/C++ • C programming language • C++ programming language • Debugging • Electronic design automation (EDA) • Embedded Systems • Heterogenous Circuits • Image Processing • Integrated circuit • Processing • single-electron transistor • specification and description language • static-induction transistor • UML
• ISBN-10: 90-481-9304-4 / 9048193044
• ISBN-13: 978-90-481-9304-2 / 9789048193042