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Timing Optimization Through Clock Skew Scheduling - Ivan S. Kourtev, Baris Taskin, Eby G. Friedman

Timing Optimization Through Clock Skew Scheduling

Buch | Softcover
266 Seiten
2010 | Softcover reprint of hardcover 1st ed. 2009
Springer-Verlag New York Inc.
978-1-4419-4377-4 (ISBN)
CHF 149,75 inkl. MwSt
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Details timing analysis and optimization techniques for circuits with level-sensitive memory elements. This title contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling.
History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe?rstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers’ desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.

VLSI Systems.- Signal Delay in VLSI Systems.- Timing Properties of Synchronous Systems.- Clock Skew Scheduling and Clock Tree Synthesis.- Clock Skew Scheduling of Level-Sensitive Circuits.- Clock Skew Scheduling for Improved Reliability.- Delay Insertion and Clock Skew Scheduling.- Practical Considerations.- Clock Skew Scheduling in Rotary Clocking Technology.- Experimental Results.

Erscheint lt. Verlag 4.11.2010
Zusatzinfo XVI, 266 p.
Verlagsort New York, NY
Sprache englisch
Maße 155 x 235 mm
Themenwelt Informatik Weitere Themen CAD-Programme
Technik Elektrotechnik / Energietechnik
ISBN-10 1-4419-4377-3 / 1441943773
ISBN-13 978-1-4419-4377-4 / 9781441943774
Zustand Neuware
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