Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Seiten
2010
|
Softcover reprint of hardcover 1st ed. 2008
Springer-Verlag New York Inc.
978-1-4419-4554-9 (ISBN)
Springer-Verlag New York Inc.
978-1-4419-4554-9 (ISBN)
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.
The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including:
• Power Reduction Fundamentals
• Energy or Average Power Reduction
• Peak Power Reduction
• Transient Power Reduction
• Leakage Power Reduction
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.
The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including:
• Power Reduction Fundamentals
• Energy or Average Power Reduction
• Peak Power Reduction
• Transient Power Reduction
• Leakage Power Reduction
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.
High-Level Synthesis Fundamentals.- Power Modeling and Estimation at Transistor and Logic Gate Levels.- Architectural Power Modeling and Estimation.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.- Conclusions and Future Direction.
| Erscheint lt. Verlag | 5.11.2010 |
|---|---|
| Zusatzinfo | 20 Illustrations, black and white; XXXII, 302 p. 20 illus. |
| Verlagsort | New York, NY |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Informatik ► Weitere Themen ► Hardware | |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 1-4419-4554-7 / 1441945547 |
| ISBN-13 | 978-1-4419-4554-9 / 9781441945549 |
| Zustand | Neuware |
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