Clock Generators for SOC Processors

Circuits and Architectures

Amr Fahim (Autor)

Buch | Softcover

246 Seiten

2010 | Softcover reprint of hardcover 1st ed. 2005
Springer-Verlag New York Inc.
978-1-4419-5470-1 (ISBN)

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This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.

Amr M. Fahim received his B.A.Sc, M.A.Sc, and Ph.D degrees from the University of Waterloo in Computer Engineering in 1996 and Electrical Engineering in 1997 and 2000, respectively. In 2000 he joined Qualcomm Inc., where he is currently working on the development of mixed-signal designs. He is the author of over 20 papers and 5 patents in this area, and has been a reviewer for the IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems II.

Phase-Locked Loop Fundamentals.- Low-Voltage Analog Cmos Design.- Jitter Analysis in Phase-Locked Loops.- Low-Jitter PLL Architectures.- Digital PLL Design.- DSP Clock Generator Architectures.- Design for Testability in PLLs.- Clock Partitioning and Skew Control.

Erscheint lt. Verlag	5.11.2010
Zusatzinfo	213 Illustrations, black and white; XVIII, 246 p. 213 illus.
Verlagsort	New York, NY
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Informatik ► Weitere Themen ► Hardware
Themenwelt	Technik ► Elektrotechnik / Energietechnik
ISBN-10	1-4419-5470-8 / 1441954708
ISBN-13	978-1-4419-5470-1 / 9781441954701
Zustand	Neuware