Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

Tim Kogel, Rainer Leupers, Heinrich Meyr (Autoren)

Buch | Softcover

186 Seiten

2010 | Softcover reprint of hardcover 1st ed. 2006
Springer (Verlag)
978-90-481-7202-3 (ISBN)

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We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

Foreword. Preface.- 1. Introduction.- 2. Embedded SOC Applications.- 3. Classification of Platform Elements.- 4. System Level Design Principles.- 5. Related Work.- 6. Methodology Overview.- 7. Unified Timing Model.- 8. MP-SOC Simulation Framework.- 9. Case Study.- 10. Summary.- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework.- List of Figures. List of Tables. References.- Index.

Erscheint lt. Verlag	19.11.2010
Zusatzinfo	XIV, 186 p.
Verlagsort	Dordrecht
Sprache	englisch
Maße	160 x 240 mm
Themenwelt	Informatik ► Grafik / Design ► Digitale Bildverarbeitung
	Mathematik / Informatik ► Informatik ► Netzwerke
	Mathematik / Informatik ► Informatik ► Software Entwicklung
	Informatik ► Theorie / Studium ► Künstliche Intelligenz / Robotik
	Informatik ► Weitere Themen ► CAD-Programme
	Technik ► Elektrotechnik / Energietechnik
ISBN-10	90-481-7202-0 / 9048172020
ISBN-13	978-90-481-7202-3 / 9789048172023
Zustand	Neuware