High Performance Embedded Architectures and Compilers

First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings

Tom Conte, Nacho Navarro, Wen-Mei W. Hwu, Mateo Valero, Theo Ungerer (Herausgeber)

Buch | Softcover

XIV, 318 Seiten

2005 | 2005
Springer Berlin (Verlag)
978-3-540-30317-6 (ISBN)

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As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.

Wen-mei W. Hwu is the Walter J. ("Jerry") Sanders III-Advanced Micro Devices Endowed Chair in Electrical and Computer Engineering in the Coordinated Science Laboratory of the University of Illinois at Urbana-Champaign. From 1997 to 1999, Dr. Hwu served as the chairman of the Computer Engineering Program at the University of Illinois. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley. His research interests are in the areas of architecture, implementation, and software for high-performance computer systems. He is the director of the OpenIMPACT project, which has delivered new compiler and computer architecture technologies to the computer industry since 1987. He also serves as the Soft Systems Theme leader of the MARCO/DARPA Gigascale Silicon Research Center (GSRC) and on the Executive Committees of both the GSRC and the MARCO/DARPA Center for Circuit and System Solutions. For his contributions to the areas of compiler optimization and computer architecture, he received the 1993 Eta Kappa Nu Outstanding Young Electrical Engineer Award, the 1994 Xerox Award for Faculty Research, the 1994 University Scholar Award of the University of Illinois, the 1997 Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the 1998 ACM SigArch Maurice Wilkes Award, the 1999 ACM Grace Murray Hopper Award, the 2001 Tau Beta Pi Daniel C. Drucker Eminent Faculty Award. He served as the Franklin Woeltge Distinguished Professor of Electrical and Computer Engineering from 2000 to 2004. He is a fellow of IEEE and ACM.

Prof. Dr. Theo Ungerer ist Professor für Systemnahe Informatik mit Schwerpunkt Kommunikationssysteme und Internet-Anwendungen am Institut für Informatik der Universität Augsburg. Zudem ist er wissenschaftlicher Direktor des Rechenzentrums und Mitglied des Lenkungsrates des IT-Servicezentrums der Universität Augsburg. Seine wissenschaftlichen Interessen gelten den Gebieten der Prozessorarchitektur sowie der eingebetteten und ubiquitären Systeme. Theo Ungerer hat über 150 wissenschaftliche Publikationen und 6 Fachbücher veröffentlicht. Er ist Mitglied des Lenkungsrates und deutscher Koordinator des EU-Exzellenznetzwerkes HiPEAC- High Performance Embedded Architectures and Compilers

Invited Program.- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications.- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges.- Software Defined Radio - A High Performance Embedded Challenge.- I Analysis and Evaluation Techniques.- A Practical Method for Quickly Evaluating Program Optimizations.- Efficient Sampling Startup for Sampled Processor Simulation.- Enhancing Network Processor Simulation Speed with Statistical Input Sampling.- II Novel Memory and Interconnect Architectures.- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation.- Streaming Sparse Matrix Compression/Decompression.- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs.- III Security Architecture.- Memory-Centric Security Architecture.- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management.- Arc3D: A 3D Obfuscation Architecture.- IV Novel Compiler and Runtime Techniques.- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations.- Induction Variable Analysis with Delayed Abstractions.- Garbage Collection Hints.- V DomainSpecificArchitectures.- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors.- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture.- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems.- A Low-Power DSP-Enhanced 32-Bit EISC Processor.

Erscheint lt. Verlag	4.11.2005
Reihe/Serie	Lecture Notes in Computer Science
Reihe/Serie	Theoretical Computer Science and General Issues
Zusatzinfo	XIV, 318 p.
Verlagsort	Berlin
Sprache	englisch
Maße	155 x 233 mm
Gewicht	472 g
Themenwelt	Informatik ► Theorie / Studium ► Algorithmen
Themenwelt	Informatik ► Weitere Themen ► Hardware
Schlagworte	Compiler • compiler techniques • Computer Architecture • dynamic compilation • Embedded Systems • high-performance architecture • memory system organization • Network Computing • network processors • Parallel Architectures • Performance Evaluation • Processor Architectures • Program Optimization • reconfigurable architectures • secured computing • security processors • system-on-chip architecture • Systems Architecture
ISBN-10	3-540-30317-0 / 3540303170
ISBN-13	978-3-540-30317-6 / 9783540303176
Zustand	Neuware