Optimal VLSI Architectural Synthesis
Area, Performance and Testability
Seiten
1991
Springer (Verlag)
978-0-7923-9223-1 (ISBN)
Springer (Verlag)
978-0-7923-9223-1 (ISBN)
Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved.
Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.
Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.
I: Introduction.- 1. Global VLSI Design Cycle.- 2. Behavioral and Structural Interfaces.- II: Review And Background.- 3. State of the Art Synthesis.- 4. Introduction to Integer Programming.- III: Optimal Architectural Synthesis With Interfaces.- 5. A Methodology for Architectural Synthesis.- 6. Simultaneous Scheduling, and Selection and Allocation Of Functional Units.- 7. Oasic: Area-Delay Constrained Architectural Synthesis.- 8. Support for Algorithmic Constructs.- 9. Interface Constraints.- 10. Oasic Synthesis Results.- IV: Testable Architectural Synthesis.- 11. Testability in Architectural Synthesis.- 12. The Catree Architectural Synthesis With Testability.- V: Summary and Future Research.- 13. Summary and Future Research.- References.
| Erscheint lt. Verlag | 31.10.1991 |
|---|---|
| Reihe/Serie | The Springer International Series in Engineering and Computer Science ; 158 |
| Zusatzinfo | XIV, 289 p. |
| Verlagsort | Dordrecht |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 0-7923-9223-X / 079239223X |
| ISBN-13 | 978-0-7923-9223-1 / 9780792392231 |
| Zustand | Neuware |
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