Static Timing Analysis for Nanometer Designs (eBook)

A Practical Approach

J. Bhasker, Rakesh Chadha (Autoren)

eBook Download: PDF

2009 | 2009
XX, 572 Seiten
Springer US (Verlag)
978-0-387-93820-2 (ISBN)

Infos

iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.

Inhalt

Contents 5
Preface 15
Introduction 21
1.1 Nanometer Designs 21
1.2 What is Static Timing Analysis? 22
1.3 Why Static Timing Analysis? 24
1.4 Design Flow 25
1.4.1 CMOS Digital Designs 25
1.4.2 FPGA Designs 28
1.4.3 Asynchronous Designs 28
1.5 STA at Different Design Phases 29
1.6 Limitations of Static Timing Analysis 29
1.7 Power Considerations 32
1.8 Reliability Considerations 33
1.9 Outline of the Book 33
STA Concepts 35
2.1 CMOS Logic Design 35
2.1.1 Basic MOS Structure 35
2.1.2 CMOS Logic Gate 36
2.1.3 Standard Cells 38
2.2 Modeling of CMOS Cells 40
2.3 Switching Waveform 43
2.4 Propagation Delay 45
2.5 Slew of a Waveform 48
2.6 Skew between Signals 50
2.7 Timing Arcs and Unateness 53
2.8 Min and Max Timing Paths 54
2.9 Clock Domains 56
2.10 Operating Conditions 59
Standard Cell Library 63
3.1 Pin Capacitance 64
3.2 Timing Modeling 64
3.2.1 Linear Timing Model 66
3.2.2 Non-Linear Delay Model 67
3.2.3 Threshold Specifications and Slew Derating 73
3.3 Timing Models - Combinational Cells 76
3.3.1 Delay and Slew Models 77
3.3.2 General Combinational Block 79
3.4 Timing Models - Sequential Cells 80
3.4.1 Synchronous Checks: Setup and Hold 82
3.4.2 Asynchronous Checks 86
3.4.3 Propagation Delay 88
3.5 State- Dependent Models 90
3.6 Interface Timing Model for a Black Box 93
3.7 Advanced Timing Modeling 95
3.7.1 Receiver Pin Capacitance 96
3.7.2 Output Current 99
3.7.3 Models for Crosstalk Noise Analysis 100
3.7.4 Other Noise Models 107
3.8 Power Dissipation Modeling 108
3.8.1 Active Power 108
3.8.2 Leakage Power 112
3.9 Other Attributes in Cell Library 114
3.10 Characterization and Operating Conditions 116
3.10.1 Derating using K-factors 117
3.10.2 Library Units 119
Interconnect Parasitics 121
4.1 RLC for Interconnect 122
4.2 Wireload Models 125
4.2.1 Interconnect Trees 128
4.2.2 Specifying Wireload Models 130
4.3 Representation of Extracted Parasitics 133
4.3.1 Detailed Standard Parasitic Format 133
4.3.2 Reduced Standard Parasitic Format 135
4.3.3 Standard Parasitic Exchange Format 137
4.4 Representing Coupling Capacitances 138
4.5 Hierarchical Methodology 139
4.6 Reducing Parasitics for Critical Nets 140
Delay Calculation 142
5.1 Overview 142
5.1.1 Delay Calculation Basics 142
5.1.2 Delay Calculation with Interconnect 144
5.2 Cell Delay using Effective Capacitance 145
5.3 Interconnect Delay 150
5.4 Slew Merging 154
5.5 Different Slew Thresholds 156
5.6 Different Voltage Domains 159
5.7 Path Delay Calculation 159
5.7.1 Combinational Path Delay 160
5.7.2 Path to a Flip- flop 162
5.7.3 Multiple Paths 164
5.8 Slack Calculation 165
Crosstalk and Noise 166
6.1 Overview 167
6.2 Crosstalk Glitch Analysis 169
6.2.1 Basics 169
6.2.2 Types of Glitches 171
6.2.3 Glitch Thresholds and Propagation 172
6.2.4 Noise Accumulation with Multiple Aggressors 179
6.2.5 Aggressor Timing Correlation 179
6.2.6 Aggressor Functional Correlation 181
6.3 Crosstalk Delay Analysis 183
6.3.1 Basics 183
6.3.2 Positive and Negative Crosstalk 186
6.3.3 Accumulation with Multiple Aggressors 188
6.3.4 Aggressor Victim Timing Correlation 188
6.3.5 Aggressor Victim Functional Correlation 190
6.4 Timing Verification Using Crosstalk Delay 190
6.4.1 Setup Analysis 191
6.4.2 Hold Analysis 192
6.5 Computational Complexity 194
6.6 Noise Avoidance Techniques 195
Configuring the STA Environment 197
7.1 What is the STA Environment? 198
7.2 Specifying Clocks 199
7.2.1 Clock Uncertainty 204
7.2.2 Clock Latency 206
7.3 Generated Clocks 208
7.4 Constraining Input Paths 219
7.5 Constraining Output Paths 223
7.6 Timing Path Groups 225
7.7 Modeling of External Attributes 228
7.7.1 Modeling Drive Strengths 229
7.7.2 Modeling Capacitive Load 232
7.8 Design Rule Checks 233
7.9 Virtual Clocks 235
7.10 Refining the Timing Analysis 237
7.10.1 Specifying Inactive Signals 238
7.10.2 Breaking Timing Arcs in Cells 239
7.11 Point-to-Point Specification 240
7.12 Path Segmentation 242
Timing Verification 244
8.1 Setup Timing Check 245
8.1.1 Flip-flop to Flip-flop Path 248
8.1.2 Input to Flip- flop Path 254
8.1.3 Flip- flop to Output Path 259
8.1.4 Input to Output Path 261
8.1.5 Frequency Histogram 263
8.2 Hold Timing Check 265
8.2.1 Flip- flop to Flip-flop Path 269
8.2.2 Input to Flip-flop Path 271
8.2.3 Flip- flop to Output Path 273
8.2.4 Input to Output Path 276
8.3 Multicycle Paths 277
8.4 False Paths 289
8.5 Half-Cycle Paths 291
8.6 Removal Timing Check 294
8.7 Recovery Timing Check 296
8.8 Timing across Clock Domains 298
8.8.1 Slow to Fast Clock Domains 298
8.8.2 Fast to Slow Clock Domains 306
8.9 Examples 312
8.10 Multiple Clocks 322
8.10.1 Integer Multiples 322
8.10.2 Non-Integer Multiples 325
8.10.3 Phase Shifted 331
Interface Analysis 334
9.1 IO Interfaces 334
9.1.1 Input Interface 335
9.1.2 Output Interface 340
9.1.3 Output Change within Window 345
9.2 SRAM Interface 353
9.3 DDR SDRAM Interface 358
9.3.1 Read Cycle 360
9.3.2 Write Cycle 365
9.4 Interface to a Video DAC 377
Robust Verification 381
10.1 On-Chip Variations 381
10.2 Time Borrowing 393
10.3 Data to Data Checks 401
10.4 Non-Sequential Checks 408
10.5 Clock Gating Checks 410
10.6 Power Management 428
10.6.1 Clock Gating 429
10.6.2 Power Gating 430
10.6.3 Multi Vt Cells 432
10.6.4 Well Bias 433
10.7 Backannotation 434
10.7.1 SPEF 434
10.7.2 SDF 434
10.8 Sign-off Methodology 434
10.9 Statistical Static Timing Analysis 438
10.9.1 Process and Interconnect Variations 439
10.9.2 Statistical Analysis 443
10.10 Paths Failing Timing? 449
10.11 Validating Timing Constraints 460
SDC 463
A. 1 Basic Commands 464
A.2 Object Access Commands 465
A.3 Timing Constraints 469
A.4 Environment Commands 477
A. 5 Multi-Voltage Commands 482
Standard Delay Format ( SDF) 483
B. 1 What is it? 484
B.2 The Format 487
B.2.1 Examples 501
B.3 The Annotation Process 511
B. 3.1 Verilog HDL 512
B.3.2 VHDL 515
B.4 Mapping Examples 517
B.5 Complete Syntax 535
Standard Parasitic Extraction Format ( SPEF) 547
C.1 Basics 547
C. 2 Format 550
C. 3 Complete Syntax 566
Bibliography 577
Index 579

Produkt-Details

• Erscheint lt. Verlag: 3.4.2009
• Zusatzinfo: XX, 572 p. 225 illus.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Cell Library • CMOS • Crosstalk • Layout • Logic • Modeling • Parasitics • semiconductor • STA Concepts • Standard • Timing • verification
• ISBN-10: 0-387-93820-6 / 0387938206
• ISBN-13: 978-0-387-93820-2 / 9780387938202