Routing Congestion in VLSI Circuits

Estimation and Optimization

Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar (Autoren)

Buch | Softcover

250 Seiten

2010 | Softcover reprint of hardcover 1st ed. 2007
Springer-Verlag New York Inc.
978-1-4419-4013-1 (ISBN)

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With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable? It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ?ow.

The Origins of Congestion.- An Introduction to Routing Congestion.- The Estimation of Congestion.- Placement-level Metrics for Routing Congestion.- Synthesis-level Metrics for Routing Congestion.- The Optimization of Congestion.- Congestion Optimization During Interconnect Synthesis and Routing.- Congestion Optimization During Placement.- Congestion Optimization During Technology Mapping and Logic Synthesis.- Congestion Implications of High Level Design.

Erscheint lt. Verlag	29.11.2010
Reihe/Serie	Series on Integrated Circuits and Systems
Zusatzinfo	XIV, 250 p.
Verlagsort	New York, NY
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Informatik ► Weitere Themen ► CAD-Programme
	Technik ► Elektrotechnik / Energietechnik
	Technik ► Nachrichtentechnik
Schlagworte	estimation • Optimization • routing congestion • Sapatnekar • VLSI circuits
ISBN-10	1-4419-4013-8 / 1441940138
ISBN-13	978-1-4419-4013-1 / 9781441940131
Zustand	Neuware